GS88032BGT-150 GSI TECHNOLOGY, GS88032BGT-150 Datasheet

GS88032BGT-150

Manufacturer Part Number

GS88032BGT-150

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS88032BGT-150.pdf (24 pages)

Specifications of GS88032BGT-150

Density

8Mb

Access Time (max)

7.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

133.3MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

18b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

130mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

32b

Number Of Words

256K

Lead Free Status / RoHS Status

Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS88018/32/36BT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.05 11/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Flow Through

Pipeline

3-1-1-1

2-1-1-1

512K x 18, 256K x 32, 256K x 36

Curr (x32/x36)

Curr (x18)

tCycle

9Mb Sync Burst SRAMs

Parameter Synopsis

1/24

-333

250

290

200

230

2.5

3.0

4.5

-300

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS88018/32/36BT is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88018/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

230

265

185

210

2.5

3.3

5.0

-250

200

230

160

185

2.5

4.0

5.5

GS88018/32/36BT-333/300/250/200/150

DDQ

-200

170

195

140

160

3.0

5.0

6.5

) pins are used to decouple output noise

-150

140

160

128

145

3.8

6.7

7.5

Unit

333 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS88032BGT-150

GS88032BGT-150 Summary of contents

Page 1

... MHz–150 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 170 140 mA 195 160 mA 6.5 7.5 ns 6.5 7.5 ns 140 128 mA 160 145 mA © 2002, GSI Technology DD ...

Page 2

... Pins marked with NC can be tied to either V Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 GS88018B 100-Pin TQFP Pinout 512K x 18 Top View These pins can also be left floating 2/ DDQ DDQ DDQ DDQ © 2002, GSI Technology ...

Page 3

... Pins marked with NC can be tied to either V Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 GS88032B 100-Pin TQFP Pinout 256K x 32 Top View These pins can also be left floating 3/ DDQ DDQ DDQ DDQ © 2002, GSI Technology ...

Page 4

... Pins marked with NC can be tied to either V Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 GS88036B 100-Pin TQFP Pinout 256K x 36 Top View These pins can also be left floating 4/ DDQ DDQ DDQ DDQ © 2002, GSI Technology ...

Page 5

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/24 © 2002, GSI Technology ...

Page 6

... Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 GS88018/32/36B Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/24 A Memory Array – © 2002, GSI Technology ...

Page 7

... Interleaved Burst Sequence 11 1st address 11 00 2nd address 01 3rd address 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 7/24 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2002, GSI Technology ...

Page 8

... C D Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 may be used in any combination with BW to write single or multiple bytes Notes and/ © 2002, GSI Technology ...

Page 9

... Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 State Diagram ADSP ADSC Key 9/24 ADV High High High High High © 2002, GSI Technology 3 ...

Page 10

... ADSP is tied high and ADV is tied low. Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 Simplified State Diagram X Deselect First Write Burst Write CR CW 10/ First Read Burst Read BW, and GW) control inputs, and © 2002, GSI Technology ...

Page 11

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 Simplified State Diagram with G X Deselect First Write Burst Write 11/ First Read Burst Read CR © 2002, GSI Technology ...

Page 12

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 12/24 Value Unit –0.5 to 4.6 V –0.5 to 4.6 V +0.5 (≤ 4.6 V max.) V DDQ +0.5 (≤ 4.6 V max +/–20 mA +/– –55 to 125 C o –55 to 125 C Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2002, GSI Technology ...

Page 13

... T 25 – not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/24 Max. Unit Notes + 0 0 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes + 0 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2002, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 14/24 50% tKC Typ. Max. Unit 30pF © 2002, GSI Technology ...

Page 15

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... GSI Technology Unit ...

Page 17

... GSI Technology Unit ...

Page 18

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 18/24 Read C+1 Read C+2 Read C+3 Cont Deselect Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2002, GSI Technology tKQX ...

Page 19

... Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 19/24 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2002, GSI Technology tKQX ...

Page 20

... Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 Sleep Mode Timing tKH tKH tKL tKL tZZS tZZH 20/24 2. The duration of SB tZZR © 2002, GSI Technology ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88018/32/36BT-333/300/250/200/150 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — 22.0 22.1 e 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7° — 21/ © 2002, GSI Technology ...

Page 22

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.05 11/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 23

... GS88018BGT-200I 512K x 18 GS88018BGT-150I 256K x 32 GS88032BGT-333I 256K x 32 GS88032BGT-300I 256K x 32 GS88032BGT-250I 256K x 32 GS88032BGT-200I 256K x 32 GS88032BGT-150I 256K x 36 GS88036BGT-333I 256K x 36 GS88036BGT-300I 256K x 36 GS88036BGT-250I 256K x 36 GS88036BGT-200I 256K x 36 GS88036BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88018BT-150IT. ...

Page 24

... Removed Preliminary banner due to qualification of parts • Added Pb-free information for TQFP Content • Corrected Pin 20 on x18 pinout (changed from V Content • Changed all Pb-free information to RoHS-compliant Content • Updated Truth Tables (pg • Changed DQP pin designation to DQ 24/ DDQ © 2002, GSI Technology ...

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