NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 25

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

PxSCTL — Serial ATA Control Register (D31:F2)
Address Offset:
Default Value:
SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software controls SATA
capabilities. Writes to the SControl register result in an action being taken by the ICH8 or the
interface. Reads from the register return the last value written to it.
Intel
®
ICH8 Family Specification Update
31:20
19:16
15:12
11:8
7:4
3:0
Bit
Bit
00000004h
Interface Power Management (IPM) — RO. Indicates the current interface state:
All other values reserved.
Current Interface Speed (SPD) — RO. Indicates the negotiated interface
communication speed.
All other values reserved.
ICH8 Supports Generation 1 communication rates (1.5 Gb/s) and Gen 2 rates
(3.0 Gb/s).
Device Detection (DET) — RO. Indicates the interface device detection and Phy
state:
All other values reserved.
Reserved
Port Multiplier Port (PMP) — RO. This field is not used by AHCI.
Select Power Management (SPM) — RO. This field is not used by AHCI.
Value
Value
Value
0h
1h
2h
6h
0h
1h
2h
0h
1h
3h
4h
Description
Device not present or communication not established
Interface in active state
Interface in PARTIAL power management state
Interface in SLUMBER power management state
Description
Device not present or communication not established
Generation 1 communication rate negotiated
Generation 2 communication rate negotiated
Description
No device detected and Phy communication not established
Device presence detected but Phy communication not established
Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
running in a BIST loopback mode
Attribute:
Size:
Description
Description
R/W, RO
32 bits
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