ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 49

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

[1]
Table 55.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
Power Down Control register (address 0354h) bit allocation
8.3.13 Power Down Control register
R/W
R/W
R/W
R/W
15
15
31
23
W
W
0
0
7
0
0
1
7
1
reserved
Table 54.
This register is used to turn off power to the internal blocks of the ISP1760 to obtain
maximum power savings.
Bit
31 to 16
15 to 0
reserved
[1]
R/W
R/W
R/W
R/W
14
14
30
22
W
W
0
0
6
0
0
1
6
0
DMA Start Address register (address 0344h) bit description
[1]
Symbol
-
START_ADDR
_DMA[15:0]
BIASEN
R/W
R/W
R/W
R/W
13
13
29
21
0
5
1
W
W
0
5
0
0
1
Rev. 08 — 13 April 2010
Table 55
CLK_OFF_COUNTER[15:8]
Description
reserved
Start Address for DMA: The start address for DMA read or write
cycles.
CLK_OFF_COUNTER[7:0]
VREG_ON
START_ADDR_DMA[15:8]
START_ADDR_DMA[7:0]
PORT3_
R/W
R/W
PD
R/W
R/W
12
4
0
1
12
28
20
W
W
0
4
0
0
0
shows the bit allocation of the register.
OC3_PWR OC2_PWR OC1_PWR
PORT2_
R/W
R/W
PD
R/W
R/W
11
1
3
0
11
27
19
W
W
0
3
0
0
1
Embedded Hi-Speed USB host controller
VBATDET_
PWR
R/W
R/W
10
2
0
R/W
R/W
0
10
26
18
W
W
0
2
0
0
0
R/W
© ST-ERICSSON 2010. All rights reserved.
R/W
1
0
R/W
R/W
25
17
9
1
W
W
9
0
1
0
1
0
reserved
ISP1760
HC_CLK_EN
[1]
R/W
R/W
R/W
R/W
0
0
49 of 105
24
16
W
W
8
0
0
0
1
0
8
1