FW82801EB Intel, FW82801EB Datasheet - Page 181

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.16.3
5.16.3.1
Intel
®
Table 78. UltraATA/33 Control Signal Redefinitions
82801EB ICH5 / 82801ER ICH5R Datasheet
Signal Descriptions
Ultra ATA/33 Protocol
Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for each IDE
device. The IDE signal protocols are significantly different under this mode than for the 8237
mode.
Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33 capable IDE
controller (e.g., the ICH5) and one or more Ultra ATA/33 capable IDE devices. It utilizes the
standard Bus Master IDE functionality and interface to initiate and control the transfer. Ultra
ATA/33 utilizes a “source synchronous” signaling protocol to transfer data at rates up to 33 MB/s.
The Ultra ATA/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16) error
checking protocol.
The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a
number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are
shown in
Write cycles are defined as transferring data from ICH5 to IDE device.
The DIOW# signal is redefined as STOP for both read and write transfers. This is always driven by
the ICH5 and is used to request that a transfer be stopped or as an acknowledgment to stop a
request from the IDE device.
The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to the
ICH5 (read). It is used by the ICH5 to signal when it is ready to transfer data and to add wait-states
to the current transaction. The DIOR# signal is redefined as STROBE for transferring data from the
ICH5 to the IDE device (write). It is the data strobe signal driven by the ICH5 on which data is
transferred during each rising and falling edge transition.
The IORDY signal is redefined as STROBE for transferring data from the IDE device to the ICH5
(read). It is the data strobe signal driven by the IDE device on which data is transferred during each
rising and falling edge transition. The IORDY signal is redefined as DMARDY# for transferring
data from the ICH5 to the IDE device (write). It is used by the IDE device to signal when it is ready
to transfer data and to add wait-states to the current transaction.
All other signals on the IDE connector retain their functional definitions during Ultra ATA/33
operation.
Signal Definition
Standard IDE
DIOW#
DIOR#
IORDY
Table
78. Read cycles are defined as transferring data from the IDE device to the ICH5.
Ultra ATA/33 Read
Cycle Definition
DMARDY#
STROBE
STOP
Ultra ATA/33 Write
Cycle Definition
DMARDY#
STROBE
STOP
Primary Channel
Intel
PDIOW#
PIORDY
PDIOR#
Signal
®
Functional Description
ICH5
Channel Signal
Intel
Secondary
SDIOW#
SIORDY
SDIOR#
®
ICH5
181