SCD128410QCE Intel, SCD128410QCE Datasheet - Page 123

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

7.4
7.4.1
Datasheet
Register Name: COR1
Register Description: Channel Option Register 1
Access: Read/Write
Parity
Bit 7
Bit
Bit
6:5
2
1
0
7
Channel Registers — Parallel Pipeline
The following five Channel Option registers control many aspects of CD1284 serial channel
operation and enable special character processing features. COR4 and COR5 specifically enable
the UNIX line discipline character handling functions.
Channel Option Register 1
Transmitter Flow Off: This bit indicates that the CD1284 has been requested to stop transmission by the
remote (received in-band flow control character XOFF). The bit is cleared when the CD1284 requests to
restart transmission (receives an XON character); the channel is either enabled or disabled, or the channel is
reset.
Transmitter Flow On: This bit is set when the CD1284 requests to restart transmission (received an XON
character). It is reset when transmission begins, when the channel is either enabled or disabled, or when the
channel is reset.
Reserved: This bit returns ‘0’ when read.
Parity Type: This bit selects the type of parity that is generated and checked if parity is enabled. ‘1’ selects
odd parity and ‘0’ selects even parity.
Parity Mode 1 and Parity Mode 0: These bits define the parity operation for both the transmitter and
receiver. The encoding is:
ParM1
Bit 6
ParM1
0
0
1
1
ParM0
Bit 5
IEEE 1284-Compatible Parallel Interface Controller — CD1284
ParM0
0
1
0
1
Ignore
Bit 4
No parity.
Force parity (odd parity = force 1, even parity = force 0).
Normal parity.
Not used.
Description
Description
Stop1
Bit 3
Stop0
Bit 2
Function
ChL1
Bit 1
8-Bit Hex Address: 08
Default Value: 00
ChL0
Bit 0
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