SCD128410QCE Intel, SCD128410QCE Datasheet - Page 164

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
164
NOTES:
1. On host I/O cycles immediately following SVCACK* cycles and writes to EOSRR, DTACK* are delayed by 20 CLKs (1 ms @
2. DTACK* sources current (drives ‘high’) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* enters the
Number
Timing
20 MHz, 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some other
form of delay generation must be used to assure that the CD1284 is not accessed until after this time period.
‘open-drain’ (high-impedance) state.
Table 28. Synchronous Timing Reference Parameters
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
12
13
14
15
16
17
18
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
Figure
29
29
29
29
29
29
29
29
29
30
31
31
30
31
32
33
32
33
32
32
33
29
32
33
33
33
Setup time, CS* and DS* to C1 rising edge
Setup time, R/W* to C1 rising edge
Setup time, address valid to C1 rising edge
C2 rising edge to data valid
DTACK* low from C3 rising edge
CS* and DS* trailing edge to data bus high-impedance
CS* and DS* inactive between host accesses
Hold time, R/W* after C3 rising edge
Hold time, address valid after C3 rising edge
Setup time, write data valid to C2 rising edge
Setup time, DS* and DGRANT* to C1 rising edge
Setup time, SVCACK* to DS* and DGRANT*
Hold time, write data valid after C3 rising edge
Propagation delay, DS* and DGRANT* to DPASS*
Falling edge DMAREQ* after rising edge CLK (DMA write/read)
Hold time, rising edge DMAREQ* after falling edge DMAACK*
(DMA write/read)
Setup time, data valid before rising edge C3 (DMA write)
Setup time, falling edge DMAACK* to falling edge C1 (DMA write/read)
DTACK* active pull-up time
Hold time, data valid after rising edge C3 (DMA write)
Hold time, data valid after rising edge C1 (DMA read)
Data valid after falling edge C1 (DMA read)
Inactive time, DMAACK* (DMA read)
2
Parameter
1
MIN
15
15
20
10
20
30
10
10
10
10
0
0
0
5
5
MAX
30
25
60
30
35
25
20
30
Datasheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns