FDC37M817-MS Standard Microsystems (SMSC), FDC37M817-MS Datasheet - Page 157

• Manufacturer Part Number: FDC37M817-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M817-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

2
Default = 0x00
on VCC POR and
VTR POR
Default = 0x00
on VTR POR
Pin Multiplex
Controls
Default = 0x02 on
VCC POR, VTR
POR and HARD
RESET
Force Disk Change
Default = 0x01 on
VCC POR
Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
UART2 FIFO
Control Shadow
NAME
Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
0xB8 R/W
(R/W)
0xC0
0xC1
0xC2
0xC3
0xC4
(R)
(R)
(R)
inputs.
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
Bit[2] IRINT: This bit is set by a transition on the IR pin
(RDX2 or IRRX as selected in CR L5-F1-B6 i.e., after
the MUX). Cleared by a read of this register.
Bit[3] Reserved
Bit[4] P12: 8042 P1.2. Cleared at source
Bit[7:5] Reserved
Bits[7:0] Reserved
Bit[0] Reserved
Bit[1] DMA 3 Select
Bit[2] Reserved
Bit[3] 8042 Select
Bit[4] Reserved
Bit[5:7] Reserved
Bit[0] Force Change 0
0 = Inactive
1 = Active
Bit[7:1] Reserved
Force Change[0] can be written to 1 but is not clearable
by software.
Force Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND
Force Change 0) OR nDSKCHG
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
157
DEFINITION
STATE
C,R
C
C
C
C