FDC37M817-MS Standard Microsystems (SMSC), FDC37M817-MS Datasheet - Page 91

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FDC37M817-MS

Manufacturer Part Number
FDC37M817-MS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of FDC37M817-MS

Pin Count
100
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37M817-MS
Manufacturer:
Microchip Technology
Quantity:
10 000
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of
which are listed below. The individual features are
explained in greater detail in the remainder of this
section.
Vocabulary
The following terms are used in this document:
assert:
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration
High performance half-duplex forward and
reverse channel
Interlocked
transfer
Optional single byte RLE compression for
improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
When a signal asserts it transitions to a
"true" state, when a signal deasserts it
transitions to a "false" state.
Registers.
Addr/RLE
compress
nBusy
PD7
D7
0
0
handshake,
intrValue
MODE
nAck
PD6
D6
0
0
for
Direction
PError
fast reliable
PD5
D5
0
Parallel Port IRQ
Parallel Port Data FIFO
nErrIntrEn
ackIntEn
ECP Data FIFO
Select
PD4
D4
Test FIFO
1
Address or RLE field
91
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication
Pword: A port word; equal in size to the width of
1
0
These terms may be considered synonymous:
Reference Document:
Capabilities Port Protocol and ISA Interface
Standard, Rev 1.14, July 14, 1993.
document is available from Microsoft.
The bit map of the Extended Parallel Port
registers is:
SelectIn
dmaEn
nFault
PD3
D3
the ISA interface. For this implementation,
PWord is always 8 bits.
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
0
A high level.
A low level.
serviceIntr
PD2
nInit
D2
0
0
Parallel Port DMA
autofd
PD1
D1
full
0
0
IEEE 1284 Extended
strobe
empty
PD0
D0
0
0
Note
2
1
1
2
2
2
This

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