FDC37M817-MS Standard Microsystems (SMSC), FDC37M817-MS Datasheet - Page 34

• Manufacturer Part Number: FDC37M817-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M817-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

RESET
There are three sources of system reset on the
FDC: the RESET_DRV pin of the FDC, a reset
generated via a bit in the DOR, and a reset
generated via a bit in the DSR. At power on, a
Power On Reset initializes the FDC. All resets
take the FDC out of the power down state.
All operations are terminated upon a RESET, and
the FDC enters an idle state. A reset while a disk
write is in progress will corrupt the data and CRC.
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the FDC waits for a
new command.
disabled by a new Configure command.
RESET_DRV Pin (Hardware Reset)
The RESET_DRV pin is a global reset and clears
all registers except those programmed by the
Specify command. The DOR reset bit is enabled
and must be cleared by the host to exit the reset
state.
BIT NO.
1,0
7
6
5
4
3
2
WP
T0
HD
DS1,0
SYMBOL
Drive polling will start unless
Write
Protected
Track 0
Head Address Indicates the status of the HDSEL pin.
Drive Select
NAME
Table 16- Status Register 3
Unused. This bit is always "0".
Indicates the status of the WP pin.
Unused. This bit is always "1".
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
Indicates the status of the DS1, DS0 pins.
34
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both
will reset the FDC core, which affects drive status
information and the FIFO circuits. The DSR reset
clears itself automatically while the DOR reset
requires the host to manually clear it. DOR reset
has precedence over the DSR reset. The DOR
reset is set automatically upon a pin reset. The
user must manually clear this reset bit in the DOR
to exit the reset state.
MODES OF OPERATION
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of the Interface Mode
bits in LD0-CRF0[3:2].
PC/AT mode
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (controls the
interrupt and DMA functions), and TC and
DENSEL become active high signals.
DESCRIPTION