PDIUSBD12PWTM STEricsson, PDIUSBD12PWTM Datasheet - Page 6

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PDIUSBD12PWTM

Manufacturer Part Number
PDIUSBD12PWTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of PDIUSBD12PWTM

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Package Type
TSSOP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PDIUSBD12PWTM
Manufacturer:
ST
Quantity:
4 500
6. Functional description
CD00222704
Product data sheet
6.1 Analog transceiver
6.2 Voltage regulator
6.3 PLL
6.4 Bit clock recovery
6.5 ST-Ericsson serial interface engine
6.6 SoftConnect
The integrated transceiver directly interfaces to USB cables through termination resistors.
A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage is
also provided as an output to connect to the external 1.5 kΩ pull-up resistor. Alternatively,
the PDIUSBD12 provides the SoftConnect technology with an integrated 1.5 kΩ pull-up
resistor.
A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows the use of a low-cost 6 MHz crystal. ElectroMagnetic Interference (EMI) is also
minimized because of the lower frequency crystal. No external components are needed
for the operation of the PLL.
The bit clock recovery circuit recovers the clock from the incoming USB data stream using
4 × over-sampling principle. It can track jitter and frequency drift specified by Universal
Serial Bus Specification Rev. 2.0.
The ST-Ericsson SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel or serial conversion, bit stuffing or discarding
stuffed bits, CRC checking or generation, PID verification or generation, address
recognition, and handshake evaluation or generation.
The connection to the USB is accomplished by connecting D+ (for full-speed USB device)
to HIGH through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up resistor
is integrated on-chip and is not connected to V
established through a command sent by the external or system microcontroller. This
allows the system microcontroller to complete its initialization sequence before deciding to
establish connection to the USB. Re-initialization of the USB bus connection can also be
performed without requiring to pull out the cable.
The PDIUSBD12 will check for USB V
established. The V
Sharing of the V
voltage as the pull-up voltage for the normally open-drain output of the DMA controller pin.
Remark: The tolerance of internal resistors is higher (25 %) than that specified in
Universal Serial Bus Specification Rev. 2.0 (5 %). The overall voltage specification for the
connection, however, can still be met with good margin. The decision to make sure of this
feature lies with users.
BUS
BUS
sensing and EOT_N can be easily accomplished by using the V
sensing is provided using pin EOT_N. For details, see
Rev. 12 — 8 April 2010
BUS
availability before the connection can be
USB peripheral controller with parallel bus
CC
by default. The connection is
PDIUSBD12
© ST-ERICSSON 2010. All rights reserved.
Section
6 of 36
BUS
5.2.

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