ISP1160BM01FE STEricsson, ISP1160BM01FE Datasheet - Page 59

• Manufacturer Part Number: ISP1160BM01FE
• Manufacturer: STEricsson

Specifications of ISP1160BM01FE

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1160-01_7
Product data sheet
10.4.5 HcμPInterruptEnable register (R/W: 25H/A5H)
Table 43.
The bits 6:0 in this register are the same as those in the HcμPInterrupt register. They are
used together with bit 0 of the HcHardwareConfiguration register to enable or disable the
bits in the HcμPInterrupt register.
On power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
Code (Hex): 25 — read
Code (Hex): A5 — write
Bit
15 to 7
6
5
4
3
2
1
0
HcμPInterrupt register: bit description
Symbol
-
ClkReady
HC
Suspended
OPR_Reg
-
AllEOT
Interrupt
ATLInt
SOFITLInt
Rev. 07 — 29 September 2009
Description
reserved
0 — no event
1 — clock is ready. After a wake-up is sent, there is a wait for clock
ready. Maximum is 1 ms, and typical is 160 μs.
0 — no event
1 — the HC has been suspended and no USB activity is sent from the
microprocessor for each ms. When the microprocessor wants to
suspend the HC, the microprocessor must write to the HcControl
register. And when all downstream devices are suspended, then the
HC stops sending SOF; the HC is suspended by having the HcControl
register written into.
0 — no event
1 — there are interrupts from HC side. Need to read HcControl and
HcInterrupt registers to detect type of interrupt on the HC (if the HC
requires the operational register to be updated).
reserved
0 — no event
1 — implies that data transfer has been completed via PIO transfer or
DMA transfer. Occurrence of internal or external EOT will set this bit.
0 — no event
1 — implies that the microprocessor must read ATL data from the HC.
This requires that the HcBufferStatus register must first be read. The
time for this interrupt depends on the number of clocks bit set for USB
activities in each ms.
0 — no event
1 — implies that SOF indicates the 1 ms mark. The ITL buffer that the
HC has handled must be read. To know the ITL buffer status, the
HcBufferStatus register must first be read. This is for the
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph in
Embedded USB host controller
Section
ISP1160/01
9.5.
© ST-ERICSSON 2009. All rights reserved.
59 of 87