PDIUSBD12D,112 STEricsson, PDIUSBD12D,112 Datasheet
PDIUSBD12D,112
Specifications of PDIUSBD12D,112
Related parts for PDIUSBD12D,112
PDIUSBD12D,112 Summary of contents
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... If you have any questions related to the document, please contact our nearest sales office or wired.support@stericsson.com. Thank you for your cooperation and understanding. ...
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PDIUSBD12 USB peripheral controller with parallel bus Rev. 10 — 23 January 2009 1. General description The PDIUSBD12 is a cost- and feature-optimized USB peripheral controller normally used in microcontroller-based systems and communicates with the system microcontroller over ...
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Fully autonomous DMA operation Integrated 320 B of multi-configuration FIFO memory Double buffering scheme for main endpoint increases throughput and eases real-time data transfer Data transfer rates: 1 MB/s achievable in bulk mode, 1 Mbit/s achievable in isochronous mode Bus-powered ...
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Block diagram This is a conceptual block diagram and does not include each individual signal. Fig 1. Block diagram 5. Pinning information 5.1 Pinning Fig 2. Pin configuration PDIUSBD12_10 Product data sheet USB peripheral controller with parallel bus UPSTREAM ...
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Pin description Table 2. Symbol DATA0 DATA1 DATA2 DATA3 GND DATA4 DATA5 DATA6 DATA7 ALE CS_N SUSPEND CLKOUT INT_N RD_N WR_N DMREQ DMACK_N EOT_N RESET_N GL_N XTAL1 XTAL2 PDIUSBD12_10 Product data sheet Pin description [1] Pin ...
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Table 2. Symbol D+ VOUT3.3 A0 [1] P: power or ground; A: analog; I: input; O: Output; O2: Output with 2 mA drive; OD4: Output open-drain with 4 mA drive; OD8: Output open-drain with 8 mA drive; IO2: Input and ...
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Functional description 6.1 Analog transceiver The integrated transceiver directly interfaces to USB cables through termination resistors. 6.2 Voltage regulator A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output ...
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GoodLink A good USB connection indication is provided through the GoodLink technology. During enumeration, the LED indicator will momentarily blink on corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be ...
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Direct Memory Access (DMA) transfer DMA allows an efficient transfer of a block of data between the host and local shared memory. Using a DMA Controller (DMAC), the data transfer between the main endpoint (endpoint 2) of the PDIUSBD12 ...
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The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In single address mode, the DMA transfer is done using the DREQ, DMACK_N, EOT_N, WR_N and RD_N control ...
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Table 3. Endpoint number Mode 0 (Non-ISO mode Mode 1 (ISO-OUT mode Mode 2 (ISO-IN mode Mode 3 (ISO-I/O mode [1] IN: input for the USB host; OUT: ...
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Main endpoint The main endpoint (endpoint number 2) is the primary endpoint for sinking or sourcing relatively large amounts of data. It implements the following features to ease this task: • Double buffering. This allows parallel operation between the ...
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Table 4. Name Set Endpoint Status Acknowledge Setup Clear Buffer Validate Buffer General commands Send Resume Read Current Frame Number 11. Command description 11.1 Command procedure There are three basic types of commands: initialization, data flow and general. Respectively, these ...
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Set Endpoint Enable Code (Hex) — D8 Transaction — write 1 B The generic or isochronous endpoints can only be enabled when the function is enabled using the Set Address/Enable command. GENERIC OR ISOCHRONOUS ENDPOINTS: Logic 1 indicates that ...
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Table 5. Bit Symbol ENDPOINT CONFIGURATION 4 SoftConnect 3 INTERRUPT MODE 2 CLOCK RUNNING 1 NO LAZYCLOCK For bit allocation, see Fig 7. Set Mode command, clock division factor byte: bit allocation PDIUSBD12_10 Product data sheet Set ...
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Table 6. Bit Symbol 7 SOF-ONLY INTERRUPT MODE 6 SET_TO_ONE CLOCK DIVISION FACTOR 11.2.4 Set DMA Code (Hex) — FB Transaction — read or write 1 B The Set DMA command is followed by one data write ...
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Table 7. Bit Symbol 7 ENDPOINT INDEX 5 INTERRUPT ENABLE 6 ENDPOINT INDEX 4 INTERRUPT ENABLE 5 INTERRUPT PIN MODE 4 AUTO RELOAD 3 DMA DIRECTION 2 DMA ENABLE DMA BURST 11.3 Data flow commands Data flow ...
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This command indicates the origin of an interrupt. The endpoint interrupt bits (bits are cleared by reading the Endpoint Last Transaction Status register through Read Last Transaction Status command. The other bits are cleared after reading Interrupt ...
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Select Endpoint Code (Hex) — Transaction — read 1 B (optional) The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, ...
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For bit allocation, see Fig 13. Read Last Transaction Status register: bit allocation Table 9. Bit Symbol 7 PREVIOUS STATUS NOT READ 6 DATA0/1 PACKET 5 SETUP PACKET ERROR CODE 0 DATA RECEIVE/TRANSMIT SUCCESS Table 10. Error ...
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Read Buffer Code (Hex) — F0 Transaction — read multiple bytes (max. 130) The Read Buffer command is followed by a number of data reads that return contents of the selected endpoint data buffer. After each read, the internal ...
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When a packet is completely received, an internal endpoint buffer full flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller has read data, it should free the buffer using the Clear Buffer command. ...
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The microcontroller must send the Acknowledge Setup command to both the IN and OUT endpoints. 11.4 General commands 11.4.1 Send Resume Code (Hex) — F6 Transaction — none Sends an upstream resume signal for 10 ms. This command is normally ...
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Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg ...
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Table 14. Static characteristics (digital pins) Symbol Parameter V HIGH-level output voltage OH Leakage current I off-state output current OZ I leakage current L I suspend current S I supply current CC Table 15. Static characteristics (AI/O pins) Symbol Parameter ...
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Table 16. Dynamic characteristics (AI/O pins; full-speed pF 1 Symbol Parameter Receiver timing: t receiver data jitter tolerance to next transition JR1 t receiver data jitter tolerance for ...
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Table 17. Dynamic characteristics (parallel interface) Symbol Parameter t write command to write data (WC WD) Read timing t CS_N (DMACK_N) LOW to RD_N LOW time CLRL t RD_N HIGH to CS_N (DMACK_N) HIGH time RHCH t A0 valid to ...
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CLRL t CLWL CS_N DMACK_N t AVRL t AVWL A0 WR_N DATA[7:0] RD_N DATA[7:0] Fig 18. Parallel interface timing (I/O and DMA) Table 18. Dynamic characteristics (DMA) Symbol Parameter Single-cycle DMA timing t DMACK_N HIGH to DMREQ HIGH time ...
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DMREQ DMACK_N RD_N/WR_N (1) EOT_N EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW. Fig 19. Single-cycle DMA timing DMREQ DMACK_N RD_N/WR_N Fig 20. Burst DMA timing DMACK_N RD_N/WR_N Fig 21. DMA terminated by EOT PDIUSBD12_10 Product ...
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Test information The dynamic characteristics of the analog I/O ports (D+ and listed in were determined using the circuit shown in Fig 22. Load for D+ and D PDIUSBD12_10 Product data sheet USB peripheral controller with ...
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Package outline SO28: plastic small outline package; 28 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...
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TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 ...
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Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 19.1 Introduction to soldering Soldering ...
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Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, ...
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MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 20. Abbreviations Table 21. Acronym ACPI CPU CRC DMA DMAC ...
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Revision history Table 22. Revision history Document ID Release date PDIUSBD12_10 20090123 Modifications: Globally changed NXP Semiconductors and NXP to ST-NXP Wireless. Also updated the legal text. PDIUSBD12_9 20060511 PDIUSBD12-08 20011220 (9397 750 08969) PDIUSBD12-07 20011127 (9397 750 08117) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration . . ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Information in this document is provided solely in connection with ST-NXP products. ST-NXP Wireless NV and its subsidiaries (“ST-NXP”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...