PDIUSBD12D,112 STEricsson, PDIUSBD12D,112 Datasheet - Page 9

• Manufacturer Part Number: PDIUSBD12D,112
• Manufacturer: STEricsson

Specifications of PDIUSBD12D,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

7. Direct Memory Access (DMA) transfer
PDIUSBD12_10
Product data sheet
DMA allows an efficient transfer of a block of data between the host and local shared
memory. Using a DMA Controller (DMAC), the data transfer between the main endpoint
(endpoint 2) of the PDIUSBD12 and the local shared memory can occur autonomously,
without the local CPU intervention.
Preceding any DMA transfer, the local CPU receives from the host the necessary setup
information and accordingly programs the DMA controller. Typically, the DMA controller is
set up for demand transfer mode, and the Byte Count register and the address counter
are programmed with the correct values. In this mode, transfers occur only when the
PDIUSBD12 requests them and are terminated when the Byte Count register reaches
zero. After the DMA controller is programmed, the DMA ENABLE bit of the PDIUSBD12 is
set by the local CPU to initiate the transfer.
The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In
single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgment by
DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active
for the number of bursts programmed in the device before going inactive. This process
continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N.
This will generate an interrupt to notify the local CPU that the DMA operation is
completed.
For the DMA read operation, the DMREQ pin will only be activated whenever the buffer is
full, signaling that the host has successfully transferred a packet to the PDIUSBD12. With
the double buffering scheme, the host can start filling up the second buffer while the first
buffer is being read out. This parallel processing increases the effective throughput. When
the host does not completely fill up the buffer (less than 64 B or 128 B for single direction
ISO configuration), the DMREQ pin will be deactivated at the last byte of the buffer,
regardless of the current DMA burst count. It will be re-asserted on the next packet with a
refreshed DMA burst count.
Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is
not full. When the buffer is filled up, the packet is sent over to the host on the next IN token
and DMREQ will be reactivated if the transfer was successful. Also, the double buffering
scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt),
the buffer needs to be completely filled up by the DMA write operation before data is sent
to the host. The only exception is at the end of DMA transfer, when the reception of the
EOT_N pin will stop the DMA write operation and the buffer content will be sent to the host
on the next IN token.
For isochronous transfers, the local CPU and DMA controller have to guarantee that they
can sink or source the maximum packet size in one USB frame (1 ms).
The assertion of pin DMACK_N automatically selects the main endpoint (endpoint 2),
regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can
be interleaved with normal I/O access to other endpoints.
The DMA operation can be terminated by resetting the DMA ENABLE register bit or the
assertion of EOT_N together with DMACK_N and either RD_N or WR_N.
Rev. 10 — 23 January 2009
USB peripheral controller with parallel bus
PDIUSBD12
© ST-NXP Wireless 2009. All rights reserved.
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