ISP1160BM,551 NXP Semiconductors, ISP1160BM,551 Datasheet - Page 84

• Manufacturer Part Number: ISP1160BM,551
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BM,551

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. DMA transfer in single-cycle mode. . . . . . . . . . . .13
Fig 11. DMA transfer in burst mode. . . . . . . . . . . . . . . . .13
Fig 12. Interrupt pin operating modes. . . . . . . . . . . . . . . .14
Fig 13. HC interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . .15
Fig 14. The ISP1160/01 HC’s USB states. . . . . . . . . . . .16
Fig 15. ISP1160/01 HC USB transaction loop. . . . . . . . .17
Fig 16. PTD data in FIFO buffer RAM.. . . . . . . . . . . . . . .19
Fig 17. HC internal FIFO buffer RAM partitions. . . . . . . .22
Fig 18. Buffer RAM data organization.. . . . . . . . . . . . . . .23
Fig 19. PTD data with DWORD alignment in buffer
Fig 20. PIO access to internal FIFO buffer RAM. . . . . . .25
Fig 21. HC time domain behavior: example 1.. . . . . . . . .29
Fig 22. HC time domain behavior: example 2.. . . . . . . . .30
Fig 23. HC time domain behavior: example 3.. . . . . . . . .30
Fig 24. Use of 15 kW pull-down resistors on downstream
Fig 25. Downstream port power management scheme. .31
Fig 26. Using an internal OC detection circuit.. . . . . . . . .32
Fig 27. Using an external OC detection circuit. . . . . . . . .33
Fig 28. ISP1160/01 suspend and resume clock scheme. 34
Fig 29. Using a 5 V supply. . . . . . . . . . . . . . . . . . . . . . . .67
Fig 30. Using a 3.3 V supply. . . . . . . . . . . . . . . . . . . . . .67
Fig 31. Oscillator circuit with external crystal. . . . . . . . . .67
Fig 32. Oscillator circuit using external oscillator. . . . . . .67
Fig 33. Internal POR timing. . . . . . . . . . . . . . . . . . . . . . .68
Fig 34. Clock with respect to the external POR. . . . . . . .68
Fig 35. Programmed interface timing. . . . . . . . . . . . . . . .74
Fig 36. Single-cycle DMA timing. . . . . . . . . . . . . . . . . . . .75
Fig 37. Burst mode DMA timing. . . . . . . . . . . . . . . . . . . .76
Fig 38. External EOT timing for single-cycle DMA. . . . . .76
Fig 39. External EOT timing for burst mode DMA.. . . . . .76
Fig 40. Typical interface circuit to Hitachi SH-3 (SH7709)
Fig 41. The ISP1160/01 software model for DSC
Fig 42. Load impedance. . . . . . . . . . . . . . . . . . . . . . . . . .79
Fig 43. LQFP64 (SOT314-2) package outline. . . . . . . . .80
Fig 44. LQFP64 (SOT414-1) package outline. . . . . . . . .81
ISP1160-01_7
Product data sheet
microprocessor and the ISP1160/01.. . . . . . . . . . .9
ISP1160/01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Accessing HC control registers.. . . . . . . . . . . . . . 11
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
RISC processor.. . . . . . . . . . . . . . . . . . . . . . . . . .77
application.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration LQFP64.. . . . . . . . . . . . . . . . . . .4
Programmed I/O interface between a
DMA interface between a microprocessor and the
Access to internal control registers. . . . . . . . . . . .10
16-bit register access cycle.. . . . . . . . . . . . . . . . . 11
32-bit register access cycle.. . . . . . . . . . . . . . . . . 11
Internal FIFO buffer RAM access cycle. . . . . . . .12
Rev. 07 — 29 September 2009
Embedded USB host controller
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
84 of 87