ISP1583BS NXP Semiconductors, ISP1583BS Datasheet
ISP1583BS
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ISP1583BS Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1583 Hi-Speed USB peripheral controller Rev. 07 — 22 September 2008 1. General description The ISP1583 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus (USB) peripheral controller. It fully complies with Rev. 2.0”, supporting data transfer at high-speed (480 ...
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... NXP Semiconductors I Automatic Hi-Speed USB mode detection and Original USB fall-back mode I Supports sharing mode I Supports I/O voltage range Supports V I High-speed DMA interface I Configurable direct access data path from the microprocessor to an ATA device I Fully autonomous and multiconfiguration DMA operation I Seven IN endpoints, seven OUT endpoints, and a fi ...
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... The package marking is the first line of text on the IC package and can be used for IC identification. ISP1583_7 Product data sheet 9 0.85 mm Marking codes Rev. 07 — 22 September 2008 ISP1583 Hi-Speed USB peripheral controller 0.8 mm [1] Marking code ISP1583BS ISP1583 1583 1583ET2 © NXP B.V. 2008. All rights reserved. Version SOT804-1 SOT543-1 SOT969-1 SOT543 ...
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... SUSPEND WAKEUP VCC1V8 The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register). (1) Pin 15 is shared by READY and IORDY. ...
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... RPU AGND 6 RREF 7 RESET_N 8 EOT DREQ 9 10 DACK DIOR 11 DIOW 12 DGND 13 INTRQ 14 READY/IORDY 15 INT 16 Pin configuration ISP1583BS (top view) ball A1 index area Pin configuration ISP1583ET and ISP1583ET2 (top view) Rev. 07 — 22 September 2008 Hi-Speed USB peripheral controller ISP1583BS ...
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... NXP Semiconductors Fig 4. 7.2 Pin description Table 3. Pin description [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 AGND 1 D2 RPU AGND 5 - RREF 6 D1 RESET_N 7 E2 EOT 8 E1 DREQ 9 F2 ISP1583_7 Product data sheet ball A1 index area Pin configuration ISP1583ET1 (top view) [2] Type Description ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 DACK 10 F1 DIOR 11 G2 DIOW 12 G1 DGND 13 H2 INTRQ 14 H1 READY IORDY INT 16 K1 [3] DA2 17 J2 CS_N 18 K2 ISP1583_7 Product data sheet [2] Type Description ISP1583ET1 E2 I/O DMA acknowledge input or output (programmable polarity) ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 RW_N RD_N DS_N WR_N [3] CS0_N 21 J4 [3] CS1_N 22 K4 AD0 23 K5 AD1 24 J5 AD2 CC(I/O) AD3 27 K7 AD4 28 J7 AD5 29 K8 AD6 30 J8 AD7 31 K9 [4] VCC1V8 32 K10 n. ISP1583_7 Product data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 MODE1 34 J10 DGND 35 H9 ALE/A0 36 H10 DATA0 37 G9 DATA1 38 G10 DATA2 39 F9 DATA3 40 F10 [ CC(I/O) DATA4 42 E10 DATA5 43 D10 DATA6 44 D9 DATA7 45 C10 DATA8 46 C9 DATA9 47 B10 ISP1583_7 Product data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 DATA10 48 A10 DATA11 49 A9 DATA12 50 B8 DATA13 51 A8 DATA14 52 B7 DATA15 CC(I/ BUS [4] VCC1V8 56 A6 XTAL2 57 A5 XTAL1 58 A4 DGND 59 B4 MODE0 [3] DA1 [ CC(3V3) ISP1583_7 Product data sheet [2] Type ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Symbol Pin ISP1583BS ISP1583ET; ISP1583ET2 BUS_ 62 B2 CONF/ [3] DA0 WAKEUP 63 A2 SUSPEND 64 C2 DGND - B9 DGND exposed die J9 pad [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. [2] All outputs and I/O pins can source 4 mA, unless otherwise specified. ...
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... NXP Semiconductors 8. Functional description The ISP1583 is a high-speed USB peripheral controller. It implements the Hi-Speed USB or the Original USB physical layer, and the packet protocol layer. It concurrently maintains USB endpoints (control IN, control OUT, and seven IN and seven OUT configurable) along with endpoint EP0 set up, which accesses the set-up buffer. The 1 “ ...
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... NXP Semiconductors Table 4. Endpoint identifier EP0SETUP EP0RX EP0TX EP1RX EP1TX EP2RX EP2TX EP3RX EP3TX EP4RX EP4TX EP5RX EP5TX EP6RX EP6TX EP7RX EP7TX The ISP1583 operates MHz crystal oscillator. An integrated 40 multiplier generates the internal sampling clock of 480 MHz. 8.1 DMA interface, DMA handler and DMA registers The DMA block can be subdivided into two blocks: DMA handler and DMA interface. The fi ...
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... NXP Semiconductors 8.2 Hi-Speed USB transceiver The analog transceiver directly interfaces to the USB cable through integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 k between pin RREF and ground to ensure an accurate current mirror that generates the Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the ISP1583 compliant to Hi-Speed USB and Original USB, supporting both the high-speed and full-speed physical layers ...
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... NXP Semiconductors The ISP1583 is a device that can initiate SRP. 8.6 NXP high-speed transceiver 8.6.1 NXP Parallel Interface Engine (PIE) In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel bidirectional data interface. The functions of the HS module also include bit-stuffing or de-stuffi ...
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... NXP Semiconductors 8.8 SoftConnect The USB connection is established by pulling pin DP (for full-speed devices) to HIGH through a 1.5 k pull-up resistor. In the ISP1583, an external 1.5 k pull-up resistor must be connected between pin RPU and 3.3 V. The RPU pin connects the pull-up resistor to pin DP, when bit SOFTCT in the Mode register is set (see hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0) ...
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... NXP Semiconductors Table 5. Bus configuration modes Pin PIO width DMA width BUS_CONF/ WIDTH = 0 DA0 LOW AD[7:0] D[7:0] HIGH A[7:0] and D[7:0] D[15:0] 8.12 Pins status Table 6 operating conditions. Table 6. ISP1583 pin status V V State CC(3V3) CC(I/ dead 3.6 V plug-out ...
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... NXP Semiconductors 8.13 Interrupt 8.13.1 Interrupt output pin The Interrupt Configuration register of the ISP1583 controls the behavior of the INT output pin. The polarity and signaling mode of the INT pin can be programmed by setting bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT ...
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DMA Interrupt Reason register GDMA_STOP EXT_EOT INT_EOT BSY_DONE TF_RD_DONE CMD_INTRQ_OK OR DMA Interrupt Enable register IE_GDMA_STOP IE_EXT_EOT IE_INT_EOT IE_BSY_DONE IE_TF_RD_DONE IE_CMD_INTRQ_OK Fig 5. Interrupt logic Interrupt Enable register IEBRST IESOF IEDMA IEP7RX IEP7TX Interrupt register BRESET SOF DMA EP7RX EP7TX ...
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... NXP Semiconductors 8.13.2 Interrupt control Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior of this bit is given in The following illustrations are only applicable for level trigger. Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT ...
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... Fig 9. ISP1583_7 Product data sheet 55 ISP1583 1 M The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see Table 3. Resistor and electrolytic or tantalum capacitor needed for V Oscilloscope reading: no resistor and capacitor in the network Oscilloscope reading: with resistor and capacitor in the network Rev. 07 — ...
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... NXP Semiconductors 8.15 Power-on reset The ISP1583 requires a minimum pulse width of 500 s. The RESET_N pin can either be connected to V externally controlled (by the microcontroller, ASIC, and so on). When V connected to the RESET_N pin, internal pulse width t The power-on reset function can be explained by viewing the dips and the V t0 — ...
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... If the ripple voltage at the input is higher than 20 mV, then use 4.7 F LOW ESR capacitors (ESR from 0 the VCC1V8 output. This is to improve the high-speed signal quality at the USB side. The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see Table 3. ...
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... NXP Semiconductors 8.16.1 Power-sharing mode Fig 13. Power-sharing mode As can be seen in the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V supplied through the power source of the system. When the USB cable is plugged in, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled. ...
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... NXP Semiconductors Table 9. ISP1583 operation Normal bus operation Core power is lost Table 10. ISP1583 operation Clock will wake up: After a resume and After a bus reset Core power is lost Table 11. ISP1583 operation Back voltage is not measured in this mode Back voltage is not an issue because core power is lost Table 12 ...
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... NXP Semiconductors 8.16.2 Self-powered mode Fig 15. Self-powered mode In self-powered mode, V Table 13. ISP1583 operation Normal bus operation No pull [1] When the USB cable is removed, SoftConnect is disabled. Table 14. ISP1583 operation Clock will wake up: After a resume and After a bus reset Clock will wake up: After detecting the presence of V Table 15 ...
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... NXP Semiconductors Table 16. ISP1583 operation SRP is not applicable SRP is possible 8.16.3 Bus-powered mode 1. 3.6 V Fig 16. Bus-powered mode In bus-powered mode (see the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V USB cable, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled ...
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... NXP Semiconductors Table 19. ISP1583 operation Back voltage is not measured in this mode Power is lost Table 20. ISP1583 operation SRP is not applicable Power is lost ISP1583_7 Product data sheet Operation truth table for back voltage compliance V CC(3V3) 3 Operation truth table for OTG V CC(3V3) 3 Rev. 07 — 22 September 2008 ...
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... NXP Semiconductors 9. Register description Table 21. Register overview Name Destination Initialization registers Address device Mode device Interrupt Configuration device OTG device Interrupt Enable device Data flow registers Endpoint Index endpoints Control Function endpoint Data Port endpoint Buffer Length endpoint Buffer Status ...
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... NXP Semiconductors Table 21. Register overview …continued Name Destination Task File 1F0 ATAPI peripheral Task File 1F1 ATAPI peripheral Task File 1F2 ATAPI peripheral Task File 1F3 ATAPI peripheral Task File 1F4 ATAPI peripheral Task File 1F5 ATAPI peripheral Task File 1F6 ...
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... NXP Semiconductors • Buffer Length • Buffer Status • Control Function • Data Port • Endpoint MaxPacketSize • Endpoint Type Remark: Write zero to all reserved bits, unless otherwise specified. 9.2 Initialization registers 9.2.1 Address register (address: 00h) This register sets the USB assigned address and enables the USB device. ...
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... NXP Semiconductors Table 24. Mode register: bit allocation Bit 15 Symbol TEST2 TEST1 Reset - Bus reset - Access R Bit 7 Symbol CLKAON SNDRSU Reset 0 Bus reset unchanged Access R/W R/W [1] Value depends on the status of the V Table 25. Bit ISP1583_7 Product data sheet TEST0 - - - - - - GOSUSP SFRESET R/W R/W pin ...
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... NXP Semiconductors Table 25. Bit The status of the chip is shown in Table 26. Bus state V on BUS V off BUS 9.2.3 Interrupt Configuration register (address: 10h) This 1-byte register determines the behavior and polarity of the INT output. The bit allocation is shown in NYET, it will generate interrupts, depending on three Debug mode fields. ...
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... NXP Semiconductors Table 27. Interrupt Configuration register: bit allocation Bit 7 Symbol CDBGMOD[1:0] Reset 1 Bus reset 1 Access R/W R/W Table 28. Bit Table 29. Value 00h 01h 1Xh [1] First NAK: the first NAK OUT token is generated after a set-up token and an ACK sequence. 9.2.4 OTG register (address: 12h) The bit allocation of the OTG register is given in Table 30 ...
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... NXP Semiconductors Table 31. Bit [1] No interrupt is designed for OTG. The V pulsing. When OTG is in progress, the V threshold or the OTG host has turned on the V during SRP, the device must complete data-line pulsing and V B_SESSION_VALID detection. OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it must provide a switch circuit to supply power to the ISP1583 core during SRP ...
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... NXP Semiconductors 9.2.4.1 Session Request Protocol (SRP) The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by V pulsing. The ISP1583 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to start SRP. 2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG register ...
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... NXP Semiconductors Table 32. Interrupt Enable register: bit allocation Bit 31 Symbol Reset - Bus reset - Access - Bit 23 Symbol IEP6TX IEP6RX Reset 0 Bus reset 0 Access R/W R/W Bit 15 Symbol IEP2TX IEP2RX Reset 0 Bus reset 0 Access R/W R/W Bit 7 Symbol IEVBUS IEDMA Reset 0 Bus reset ...
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... NXP Semiconductors Table 33. Bit 9.3 Data flow registers 9.3.1 Endpoint Index register (address: 2Ch) The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte, and the bit allocation is shown in The following registers are indexed: • ...
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... NXP Semiconductors Table 35. Bit Table 36. Buffer name SETUP Control OUT Control IN Data OUT Data IN 9.3.2 Control Function register (address: 28h) The Control Function register performs the buffer management on endpoints. It consists of 1 byte, and the bit configuration is given in validate any enabled endpoint. Before accessing this register, the Endpoint Index register must fi ...
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... NXP Semiconductors Table 38. Bit 9.3.3 Data Port register (address: 20h) This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed endpoint. The bit allocation is shown in Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto incremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in the TX FIFO ...
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... NXP Semiconductors buffer is automatically validated. The data packet will then be sent on the next IN token. When it is necessary to validate the endpoint whose byte count is less than MaxPacketSize, it can be done using the Control Function register (bit VENDP) or the Buffer Length register. Remark: The buffer can automatically be validated by using the Buffer Length register ...
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... NXP Semiconductors Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register need not be filled. This is because the transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be automatically validated because the last packet is also of MaxPacketSize. ...
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... NXP Semiconductors Table 43 Table 43. Buffer Status register: bit allocation Bit 7 Symbol Reset - Bus reset - Access - Table 44. Bit 9.3.6 Endpoint MaxPacketSize register (address: 04h) This register determines the maximum packet size for all endpoints, except set-up token buffer, control IN and control OUT. The register contains 2 bytes, and the bit allocation is ...
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... NXP Semiconductors Table 46. Bit The ISP1583 supports all the transfers given in Rev. 2.0”. Each programmable FIFO can be independently configured using its Endpoint MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN plus OUT), including set-up token buffer, control IN and control OUT, must not exceed 8192 bytes ...
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... NXP Semiconductors Table 48. Bit 9.4 DMA registers Two types of Generic DMA transfers and three types of IDE-specified transfers can be done by writing the proper opcode in the DMA Command register. Control bits are given in transfers). GDMA read/write (opcode = 00h/01h) — Generic DMA slave mode. Depending on the MODE[1:0] bits set in the DMA Confi ...
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... NXP Semiconductors In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. The DMA transfer will start once the DMA command is issued. Any of the following three ways will terminate this DMA transfer: • ...
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... NXP Semiconductors Table 49. Control bits DMA Hardware register ENDIAN[1:0] EOT_POL MASTER ACK_POL, DREQ_POL, WRITE_POL, READ_POL Table 50. Control bits DMA Configuration register ATA_MODE DMA_MODE[1:0] PIO_MODE[2:0] DMA Hardware register MASTER Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the other control signals are not 3-stated ...
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... NXP Semiconductors Table 52. Bit Table 53. Code 00h 01h 02h to 05h 06h 07h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h ISP1583_7 Product data sheet DMA Command register: bit description Symbol Description DMA_CMD[7:0] DMA command code, see PIO read or write that started using the DMA Command register only performs a 16-bit transfer ...
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... NXP Semiconductors Table 53. Code 11h 12h 13h 14h to 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h to FFh 9.4.2 DMA Transfer Counter register (address: 34h) This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in For IN endpoint — ...
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... NXP Semiconductors If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when it reaches zero. Table 54. DMA Transfer Counter register: bit allocation Bit 31 Symbol Reset 0 Bus reset 0 Access R/W Bit 23 Symbol Reset 0 Bus reset 0 Access R/W Bit 15 Symbol Reset ...
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... NXP Semiconductors Bit 7 Symbol DIS_ XFER_CNT Reset 0 Bus reset 0 Access R/W Table 57. Bit [1] The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is, after configuring the DMA Configuration register). ISP1583_7 Product data sheet ...
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... NXP Semiconductors [2] PIO read or write that started using the DMA Command register only performs 16-bit transfer. 9.4.4 DMA Hardware register (address: 3Ch) The DMA Hardware register consists of 1 byte. The bit allocation is shown in This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and DIOW) and DMA mode (master or slave) ...
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... NXP Semiconductors Table 59. Bit 9.4.5 Task File registers (addresses: 40h to 4Fh) These registers allow direct access to the internal registers of an ATAPI peripheral using PIO mode. The supported Task File registers and their functions are shown in The correct peripheral register is automatically addressed using pins CS1_N, CS0_N, DA2, MODE0/DA1 and BUS_CONF/DA0 (see Table 60 ...
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... NXP Semiconductors In 8-bit bus mode, 16-bit Task File register 1F0 requires two consecutive write/read accesses before the proper PIO write/read is generated on the IDE interface. The first byte is always the lower byte (LSByte). Other Task File registers can directly be accessed. Writing to Task File registers can be done in any order, except for the Task File register 1F7, which must be written last ...
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... NXP Semiconductors Table 67. Task File 1F5 register (address: 4Ch): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH. Bit 7 Symbol Reset 0 Bus reset 0 Access R/W R/W Table 68. Task File 1F6 register (address: 4Dh): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW. ...
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... NXP Semiconductors 9.4.6 DMA Interrupt Reason register (address: 50h) This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. On detecting the interrupt, the external microprocessor must read the DMA Interrupt Reason register and mask it with the corresponding bits in the DMA Interrupt Enable register to determine the source of the interrupt ...
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... NXP Semiconductors Table 73. Bit Table 74. INT_EOT 9.4.7 DMA Interrupt Enable register (address: 54h) This 2-byte register controls the interrupt generation of the source bits in the DMA Interrupt Reason register (see description is given in Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is disabled, with values turning to logic 0 ...
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... NXP Semiconductors Table 76. DMA Endpoint register: bit allocation Bit 7 Symbol Reset - Bus reset - Access - Table 77. Bit The DMA Endpoint register must not reference the endpoint that is indexed by the Endpoint Index register (2Ch) at any time. Doing so will result in data corruption. Therefore, if the DMA Endpoint register is unused, point unused endpoint. If the DMA Endpoint register, however, is pointed to an active endpoint, the fi ...
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... NXP Semiconductors Fig 17. Programmable strobe timing 9.4.10 DMA Burst Counter register (address: 64h) Table 80 Table 80. DMA Burst Counter register: bit allocation Bit 15 14 Symbol reserved Reset - Bus reset - Access - Bit 7 6 Symbol Reset 0 0 Bus reset 0 0 Access R/W R/W Table 81. ...
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... NXP Semiconductors Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register. Table 82. ...
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... NXP Semiconductors Table 83. Bit 9.5.2 Chip ID register (address: 70h) This read-only register contains the chip identification and hardware version numbers. The firmware must check this information to determine functions and features supported. The register contains 3 bytes, and the bit allocation is shown in Table 84 ...
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... NXP Semiconductors Table 85. Bit 9.5.3 Frame Number register (address: 74h) This read-only register contains the frame number of the last successfully received Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in Table 86. In case of 8-bit access, the register content is returned lower byte first. ...
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... NXP Semiconductors Table 89. Bit 9.5.5 Unlock Device register (address: 7Ch) To protect registers from getting corrupted when the ISP1583 goes into suspend, the write operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when the chip resumes, the Unlock Device command must first be issued to this register before attempting to write to the rest of the registers ...
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... NXP Semiconductors Table 92. Test Mode register: bit allocation Bit 7 Symbol FORCEHS Reset 0 Bus reset unchanged Access R/W Table 93. Bit ISP1583_7 Product data sheet reserved FORCEFS - - unchanged - - R/W Test Mode register: bit description Symbol Description FORCEHS Force High-Speed: Logic 1 forces the hardware to high-speed mode only and disables the chirp detection logic ...
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... NXP Semiconductors 10. Limiting values Table 94. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) CC(3V3) V input/output supply voltage CC(I/O) V input voltage I I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg [1] The maximum value for 5 V tolerant pins ...
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... NXP Semiconductors Table 96. Static characteristics: supply pins V = 3 CC(3V3) GND Symbol Parameter I supply current on pin V CC(I/O) Regulated supply voltage V supply voltage (1.8 V) CC(1V8) [1] I test condition: device set up under the test mode vector and I/O is subjected to external conditions. CC(I/O) Table 97. ...
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... NXP Semiconductors Table 99. Static characteristics: analog I/O pins DP and 3 CC(3V3) GND Symbol Parameter Schmitt-trigger inputs V positive-going threshold voltage th(LH) V negative-going threshold voltage th(HL) V hysteresis voltage hys Output levels V LOW-level output voltage OL V HIGH-level output voltage OH Leakage current I OFF-state leakage current ...
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... NXP Semiconductors Table 101. Dynamic characteristics: analog I/O pins DP and 3 CC(3V3) GND Figure 38; unless otherwise specified. Symbol Parameter Driver characteristics Full-speed mode t rise time FR t fall time FF FRFM differential rise time/fall time matching V output signal crossover voltage CRS ...
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... NXP Semiconductors T PERIOD 3.3 V differential data lines the bit duration corresponding to the USB data rate. PERIOD Fig 19. Receiver differential data jitter Fig 20. Receiver SE0 width tolerance 13.1 Register access timing Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. ...
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... NXP Semiconductors Table 102. ISP1583 register access timing parameters: separate address and data buses CC(I/O) CC(3V3) Symbol Parameter t CS_N LOW to RW_N/RD_N LOW delay SLRL Writing t DS_N/WR_N LOW pulse width WLWH t address set-up time before DS_N/WR_N LOW AVWL t address hold time after DS_N/WR_N HIGH ...
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... NXP Semiconductors DS_N/WR_N, RW_N/RD_N READY/IORDY Fig 22. ISP1583 ready signal timing 13.1.1.2 Freescale mode MODE0/DA1 = LOW: Freescale mode; see Table 103. ISP1583 register access timing parameters: separate address and data buses CC(I/O) CC(3V3) Symbol Parameter Reading or writing t DS_N/WR_N LOW pulse width ...
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... NXP Semiconductors CS_N AD [ 7:0 ] (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DS_N/WR_N RW_N/RD_N Fig 23. ISP1583 register access timing: separate address and data buses (Freescale mode) DS_N/WR_N READY/IORDY Fig 24. ISP1583 ready signal timing ISP1583_7 Product data sheet T cy(RW) t AVWL t t I1VI2L DVWH t WLWH ...
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... NXP Semiconductors (1) Programmable polarity: shown as active LOW. Fig 25. EOT timing in generic processor mode 13.1.2 Split bus mode 13.1.2.1 ALE function 8051 mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = LOW: ALE function – MODE0/DA1 = HIGH: 8051 mode; see Table 104. ISP1583 register access timing parameters: multiplexed address/data bus 3.6 V ...
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... NXP Semiconductors CS_N (read 7:0 ] RW_N/RD_N (write 7:0 ] DS_N/WR_N ALE/A0 Fig 26. ISP1583 register access timing: multiplexed address/data bus (8051 mode) Freescale mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = LOW: ALE function – MODE0/DA1 = LOW: Freescale mode; see Table 105. ISP1583 register access timing parameters: multiplexed address/data bus 3.6 V ...
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... NXP Semiconductors CS_N (read 7:0 ] (write 7 I1VLL DS_N/WR_N RW_N/RD_N ALE/A0 Fig 27. ISP1583 register access timing: multiplexed address/data bus (Freescale mode) 13.1.2.2 A0 function 8051 mode • BUS_CONF/DA0 = LOW: split bus mode • MODE1 = HIGH: A0 function – MODE0/DA1 = HIGH: 8051 mode; see Table 106. ISP1583 register access timing parameters: multiplexed address/data bus 3.6 V ...
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... NXP Semiconductors Table 106. ISP1583 register access timing parameters: multiplexed address/data bus CC(I/O) CC(3V3) Symbol Parameter t DS_N/WR_N HIGH (address) to DS_N/WR_N WHWH HIGH (data) delay General T read or write cycle time cy(RW) t A0WL ALE/A0 CS_N (read 7:0 ] address RW_N/RD_N t AVWH DS_N/WR_N (write 7:0 ] ...
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... NXP Semiconductors Table 107. ISP1583 register access timing parameters: multiplexed address/data bus CC(I/O) CC(3V3) Symbol Parameter t DS_N/WR_N HIGH to CS_N HIGH delay RHSH t DS_N/WR_N LOW pulse width RLRH t DS_N/WR_N HIGH (address) to DS_N/WR_N WHRH HIGH (data read) delay Writing t ALE/A0 set-up time before DS_N/WR_N LOW ...
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... NXP Semiconductors t A0WL ALE/A0 CS_N (read 7:0 ] RW_N/RD_N t AVWH DS_N/WR_N (write 7:0 ] DS_N/WR_N RW_N/RD_N Fig 29. ISP1583 register access timing: multiplexed address/data bus (A0 function and Freescale mode) (1) Programmable polarity: shown as active LOW. Fig 30. EOT timing in split bus mode ISP1583_7 Product data sheet ...
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... NXP Semiconductors 13.2 DMA timing 13.2.1 PIO mode Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. Table 108. PIO mode timing parameters CC(I/O) CC(3V3) Symbol Parameter T read or write cycle time cy1(min) t address to DIOR or DIOW on set-up ...
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... NXP Semiconductors (1) device address valid (4) DIOR, DIOW (2) (write) DATA [ 7:0 ] (2) (read) DATA [ 7:0 ] (3a) HIGH READY/IORDY (3b) READY/IORDY (3c) READY/IORDY (1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0. (2) The data bus width depends on the PIO access command used. The Task File register access uses 8 bits (DATA[7:0]), except for Task File register 1F0 that uses 16 bits (DATA[15:0]) ...
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... NXP Semiconductors 13.2.2 GDMA slave mode • Bits MODE[1:0] = 00: data strobes DIOR (read) and DIOW (write); see • Bits MODE[1:0] = 01: data strobes DIOR (read) and DACK (write); see • Bits MODE[1:0] = 10: data strobes DACK (read and write); see Table 109. GDMA slave mode timing parameters 3.6 V ...
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... NXP Semiconductors (2) DREQ t t su1 (1) DACK (1) DIOR or DIOW (read) DATA [ 15:0 ] (write) DATA [ 15:0 ] DREQ is asserted for every transfer. Data strobes: DIOR (read), DACK (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 33. GDMA slave mode timing: DIOR (master) or DACK (slave) ...
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... NXP Semiconductors 13.2.3 MDMA mode Table 110. MDMA mode timing parameters CC(I/O) CC(3V3) Symbol Parameter T read/write cycle time cy1(min) t DIOR or DIOW pulse width w1(min) t data valid delay after DIOR on d1(max) t data hold time after DIOR off h3(min) t data set-up time before DIOR or DIOW off ...
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... NXP Semiconductors 14. Application information Fig 36. Typical interface connections for generic processor mode Fig 37. Typical interface connections for split bus mode (slave mode) 15. Test information The dynamic characteristics of analog I/O ports DP and DM are determined using the circuit shown in ISP1583_7 Product data sheet ...
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... NXP Semiconductors Fig 38. Load impedance for the DP and DM pins (full-speed mode) ISP1583_7 Product data sheet DUT In full-speed mode, an internal 1.5 k pull-up resistor is connected to pin DP. Rev. 07 — 22 September 2008 ISP1583 Hi-Speed USB peripheral controller test point mgt495 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 16. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 0.85 mm terminal 1 index area terminal 1 64 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.05 0.80 0. 0.00 0.65 0.18 OUTLINE VERSION IEC SOT804 Fig 39. Package outline SOT804-1 (HVQFN64) ...
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... NXP Semiconductors TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 0.85 0.35 mm 1.1 0.15 0.75 0.25 OUTLINE VERSION IEC SOT543 Fig 40. Package outline SOT543-1 (TFBGA64) ...
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... NXP Semiconductors TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.85 0.3 mm 1.1 0.15 0.75 0.2 OUTLINE VERSION IEC SOT969 Fig 41. Package outline SOT969-1 (TFBGA64) ...
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... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 42. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 113. Abbreviations Acronym ACK ACPI ASIC ATA ATAPI CRC DMA EMI ESR ...
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... NXP Semiconductors Table 113. Abbreviations Acronym OTG PCB PHY PID PIE PIO PLL POR SE0 SIE SRP TTL USB 19. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB Specification Rev. 1.3 [3] Using ISP1582 composite device application with alternate settings ...
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... NXP Semiconductors 20. Revision history Table 114. Revision history Document ID Release date ISP1583_7 20080922 • Modifications: Added ISP1583ET2. • Added Section 5 • Added Table 4 “Endpoint access and • Figure 16 “Bus-powered • Removed Section 7.9 “Clear buffer”. • Table 24 “Mode register: bit • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4. Endpoint access and programmability . . . . . . .13 Table 5. Bus configuration modes . . . . . . . . . . . . . . . . .17 Table 6. ISP1583 pin status . . . . . . . . . . . . . . . . . . . . . .17 Table 7. ISP1583 output pin status . . . . . . . . . . . . . . . .17 Table 8. Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 9. Operation truth table for SoftConnect . . . . . . .25 Table 10. Operation truth table for clock off during suspend ...
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... NXP Semiconductors Table 78. DMA Strobe Timing register: bit allocation . . .58 Table 79. DMA Strobe Timing register: bit description . .58 Table 80. DMA Burst Counter register: bit allocation . . .59 Table 81. DMA Burst Counter register: bit description . .59 Table 82. Interrupt register: bit allocation . . . . . . . . . . . .60 Table 83. Interrupt register: bit description . . . . . . . . . . .60 Table 84. Chip ID register: bit allocation . . . . . . . . . . . . .61 Table 85 ...
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... NXP Semiconductors 24. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ISP1583BS (top view Fig 3. Pin configuration ISP1583ET and ISP1583ET2 (top view Fig 4. Pin configuration ISP1583ET1 (top view Fig 5. Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Fig 6. Behavior of bit GLINTENA . . . . . . . . . . . . . . . . . .20 Fig 7. Resistor and electrolytic or tantalum capacitor needed for V sensing ...
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... NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . 12 8.1 DMA interface, DMA handler and DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.2 Hi-Speed USB transceiver . . . . . . . . . . . . . . . 14 8.3 MMU and integrated RAM ...
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... NXP Semiconductors 17 Soldering of SMD packages . . . . . . . . . . . . . . 89 17.1 Introduction to soldering . . . . . . . . . . . . . . . . . 89 17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 89 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 89 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 90 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 91 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 93 21 Legal information 21.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 94 21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 22 Contact information Tables ...