ISP1581BD NXP Semiconductors, ISP1581BD Datasheet - Page 41

• Manufacturer Part Number: ISP1581BD
• Manufacturer: NXP Semiconductors

Specifications of ISP1581BD

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 49:
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L.
Table 50:
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H.
Table 51:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Task File register 3F6 (address: 4EH): bit allocation
Task File register 3F7 (address: 4FH): bit allocation
DMA Interrupt Reason register: bit allocation
1F0_WF_E
R/W
R/W
15
7
7
7
0
0
-
-
9.4.7 DMA Interrupt Reason register (address: 50H)
1F0_WF_F
This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed
after a DMA command has been executed. An interrupt source is cleared by writing a
logic 1 to the corresponding bit. The bit allocation is given in
reserved
Table 52:
Bit
15 to 13 -
12
11
10
R/W
R/W
14
6
6
6
0
0
-
-
Symbol
ODD_IND
EXT_EOT
INT_EOT
DMA Interrupt Reason Register: bit description
1F0_RF_E
R/W
R/W
13
5
5
5
0
0
-
-
alternate status/command (ATA or ATAPI)
Rev. 06 — 23 December 2004
drive address (ATA) or reserved (ATAPI)
READ_1F0
ODD_IND
R/W
R/W
12
4
4
0
0
4
0
0
Description
reserved
A logic 1 indicates that the last packet with odd bytes has
been transferred from the OUT token buffer to the DMA. This
is applicable only for the OUT token data in the DMA slave
mode. It has no meaning for the IN token data. Refer to the
document Using the Odd Bit Indicator for DMA .
A logic 1 indicates that an external EOT is detected. This is
applicable only in GDMA slave mode.
A logic 1 indicates that an internal EOT is detected. see
Table
R/W
R/W
00H
00H
00H
00H
53.
EXT_EOT
DONE
BSY_
R/W
R/W
11
3
3
0
0
3
0
0
Hi-Speed USB peripheral controller
INT_EOT
TF_RD_
DONE
R/W
R/W
10
2
2
0
0
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
INTRQ_OK
PENDING
INTRQ_
CMD_
R/W
R/W
1
1
9
0
0
1
0
0
51.
ISP1581
XFER_OK
reserved
DMA_
R/W
R/W
0
0
8
0
0
0
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