LH7A400N0F000B3A,5 NXP Semiconductors, LH7A400N0F000B3A,5 Datasheet - Page 23

• Manufacturer Part Number: LH7A400N0F000B3A,5
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0F000B3A,5

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.89V
• Package Type: LFBGA
• Pin Count: 256
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

32-Bit System-on-Chip
External Bus Interface
LCD controller and DMA engine access to an external
memory system. The LCD controller has access to an
internal frame buffer in embedded SRAM and an exten-
sion buffer in Synchronous Memory for large displays.
The processor and DMA engine share the main system
bus, providing access to all external memory devices
and the embedded SRAM frame buffer.
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 7.
Embedded SRAM
LH7A400 is 80 kB. This Embedded memory is
designed to be used for storing code, data, or LCD
frame data and to be contiguous with external SDRAM.
The 80 kB is large enough to store a QVGA panel (320
× 240) at 8 bits per pixel, equivalent to 70 kB of informa-
tion.
overall power consumed in any application that uses
the LH7A400. Normally, the system has to perform
external accesses to acquire this data. The LCD con-
troller is designed to automatically use an overflow
frame buffer in SDRAM if a larger screen size is
required. This overflow buffer can be located on any
Preliminary data sheet
The external bus interface allows the ARM922T,
An arbitration unit ensures that control over the
The amount of Embedded SRAM contained in the
Containing the frame buffer on chip reduces the
E000.0000
D000.0000
C000.0000
B001.4000
B000.0000
F000.0000
8000.3800
8000.2000
8000.0000
7000.0000
6000.0000
5000.0000
4000.0000
3000.0000
2000.0000
1000.0000
0000.0000
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
ASYNCHRONOUS MEMORY (nCS0)
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
EMBEDDED SRAM
RESERVED
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
SYNCHRONOUS ROM (nSCS3)
SYNCHRONOUS MEMORY BOOT
Figure 6. Memory Mapping for Each Boot Mode
Rev. 01 — 16 July 2007
NXP Semiconductors
4 kB page boundary in SDRAM, allowing software to
set the MMU (in the LCD controller) page tables such
that the two memory areas appear contiguous. Byte,
Half-Word and Word accesses are permissible.
Asynchronous Memory Controller
rated as part of the memory controller to provide an
interface between the AMBA AHB system bus and
external (off-chip) memory devices.
port for up to eight independently configurable memory
banks simultaneously. Each memory bank is capable
of supporting:
• SRAM
• ROM
• Flash EPROM
• Burst ROM memory.
16-, or 32-bit external memory data paths. The memory
controller supports only little-endian operation.
• Non-burst read and write accesses only to high-
• Non-burst write accesses, nonburst read accesses
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
speed CMOS static RAM.
and asynchronous page mode read accesses to
fast-boot block flash memory.
SYNCHRONOUS MEMORY (nSCS3)
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
EMBEDDED SRAM
RESERVED
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
ASYNCHRONOUS ROM (nCS0)
The Asynchronous memory controller is incorpo-
The Asynchronous Memory Controller provides sup-
Each memory bank may use devices using either 8-,
The memory banks can be configured to support:
ASYNCHRONOUS MEMORY BOOT
256MB
256MB
256MB
256MB
80KB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
LH7A400-6
LH7A400
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