MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 166

• Manufacturer Part Number: MC9S08QG8CPBE
• Manufacturer: Freescale

Specifications of MC9S08QG8CPBE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 16
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

Inter-Integrated Circuit (S08IICV1)
11.3.5
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IICD will not initiate the receive.
Reading the IICD will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7–bit 1) concatenated with the required
R/W bit (in position bit 0).
164
Reset
Field
DATA
7:0
W
R
IIC Data I/O Register (IICD)
Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
0
7
When transmitting out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
0
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Table 11-7. IICD Register Field Descriptions
Figure 11-7. IIC Data I/O Register (IICD)
0
5
NOTE
0
4
Description
DATA
3
0
0
2
Freescale Semiconductor
0
1
0
0