MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 78

• Manufacturer Part Number: MC9S08QG8CPBE
• Manufacturer: Freescale

Specifications of MC9S08QG8CPBE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 16
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

1
Chapter 5 Resets, Interrupts, and General System Control
5.8.10
This high page register is used to report the status of the low voltage warning function and to select the
low voltage detect trip voltage.
Any other
76
LVWF will be set in the case when V
LVWACK
reset:
POR:
LVWF
LVWV
LVD:
Field
LVDV
7
6
5
4
W
R
LVWF
System Power Management Status and Control 3 Register
(SPMSC3)
Figure 5-12. System Power Management Status and Control 3 Register (SPMSC3)
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status. Writing a 1 to
LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
0
0
0
7
1
1
1
= Unimplemented or Reserved
LVWACK
0
0
0
0
6
Table 5-14. SPMSC3 Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Supply
LVD
LVW
LVDV
LVD
LVW
transitions below the trip point or after reset and V
U
U
0
5
= V
= V
= V
= V
LVDL
LVWL
LVDH
LVWH
).
).
).
).
LVWV
U
U
0
4
Description
3
0
0
0
0
U= Unaffected by reset
0
0
0
0
2
Supply
is already below V
Freescale Semiconductor
0
0
0
0
LVD
1
LVW
).
).
0
0
0
0
LVW
0
.