EE80C188XL12 S F12 Intel, EE80C188XL12 S F12 Datasheet - Page 45

• Manufacturer Part Number: EE80C188XL12 S F12
• Manufacturer: Intel

Specifications of EE80C188XL12 S F12

• Family Name: Intel186
• Device Core: 80188
• Device Core Size: 16b
• Frequency (max): 12MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Compliant

INSTRUCTION SET SUMMARY
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
LOGIC (Continued)
XOR
Reg memory and register to either
Immediate to register memory
Immediate to accumulator
NOT
STRING MANIPULATION
MOVS
CMPS
SCAS
LODS
STOS
INS
OUTS
Repeated by count in CX (REP REPE REPZ REPNE REPNZ)
MOVS
CMPS
SCAS
LODS
STOS
INS
OUTS
CONTROL TRANSFER
CALL
Direct within segment
Register memory
indirect within segment
Direct intersegment
Indirect intersegment
JMP
Short long
Direct within segment
Register memory
indirect within segment
Direct intersegment
Indirect intersegment
Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
Input byte wd from DX port
e
Input string
Unconditional jump
Invert register memory
Exclusive or
Store byte wd from AL AX
Store string
Call
Scan byte word
Load byte wd to AL AX
Output byte wd to DX port
Scan string
Load string
Output string
Compare byte word
Compare string
Move byte word
Move string
Function
0 0 1 1 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 1 0 1 0 w
1 1 1 1 0 1 1 w
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
0 1 1 0 1 1 0 w
0 1 1 0 1 1 1 w
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 z
1 1 1 1 0 0 1 z
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1
1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1
1 1 1 0 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 1 1 1
1 1 1 0 1 0 1 0
1 1 1 1 1 1 1 1
(Continued)
mod 1 1 0 r m
mod 0 1 0 r m
mod 0 1 0 r m
mod 0 1 1 r m
mod 1 0 0 r m
mod 1 0 1 r m
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
0 1 1 0 1 1 0 w
0 1 1 0 1 1 1 w
mod reg r m
disp-low
disp-low
disp-low
data
segment selector
segment selector
segment offset
segment offset
Format
data if w
(mod
(mod
disp-high
disp-high
data
i
i
e
11)
11)
1
data if w
e
1
80C186XL
80C186XL 80C188XL
Cycles
5
5
6
Clock
8
6
8
8
13 19
11 17
3 10
4 16
3 10
a
a
a
3 4
a
a
a
a
14
22
15
12
10
14
14
15
23
38
14
14
14
26
22n
15n
11n
8n
9n
8n
8n
80C188XL
Cycles
5
5
6
Clock
8
6
8
8
17 27
11 21
3 10
4 16
3 10
a
a
a
3 4
a
a
a
a
14
22
15
12
10
14
14
19
31
54
14
14
14
34
22n
15n
11n
8n
9n
8n
8n
Comments
8 16-bit
45