SAA7113HV2 NXP Semiconductors, SAA7113HV2 Datasheet - Page 6

SAA7113HV2

Manufacturer Part Number
SAA7113HV2
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7113HV2

Video Resolution (max)
720Pixels
Pin Count
44
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
9397 750 14232
Product data sheet
Table 3:
Symbol
VPO7 to
VPO4
V
LLC
V
VPO3 to
VPO0
SDA
SCL
RTCO
RTS0
RTS1
V
V
V
XTAL
XTALI
V
V
V
TDO
TCK
TDI
TMS
SSDE1
DDDE1
SSDI
DDDI
SSDA
DDDA
DDDE2
SSDE2
Pin
12 to 15 O
16
17
18
19 to 22 O
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Pin description
Type
P
O
P
I/O
I(/O)
(I/)O
(I/)O
I/O
P
P
P
O
I
P
P
P
O
I
I
I
Rev. 02 — 9 May 2005
…continued
Description
digital VPO-bus output signal; higher bits of the 8-bit output bus. The
output data types of the VPO-bus are controlled via I
LCR2 to LCR24 (see
of the digitized input signal are connected to these outputs,
configured by the I
ground 1 or digital supply voltage input E (external pad supply)
line-locked system clock output (27 MHz)
digital supply voltage E1 (external pad supply 1; 3.3 V)
digital VPO-bus output signal; lower bits of the 8-bit output bus. The
output data types of the VPO-bus are controlled via I
LCR2 to LCR24 (see
of the digitized input signal are connected to these outputs,
configured by the I
serial data input/output (I
serial clock input (I
real-time control output; contains information about actual system
clock frequency, field rate, odd/even sequence, decoder status,
subcarrier frequency and phase and PAL sequence (see external
document “RTC Functional Description” , available on request); the
RTCO pin is enabled via I
Remark: this pin is also used as an input pin for test purposes and
has an internal pull-down resistor; do not connect any pull-up resistor
to this pin
real-time signal output 0: multifunctional output, controlled by I
bits RTSE03 to RTSE00 (see
power-on or CE driven reset, defines which I
used; LOW = 48h for write, 49h for read, external pull-down resistor
of 3.3 k is needed and HIGH = 4Ah for write, 4Bh for read, default
slave address (default, internal pull-up).
real-time signal I/O terminal 1: multifunctional output, controlled by
I
ground for internal digital core supply
internal core supply (3.3 V)
digital ground for internal crystal oscillator
second terminal of crystal oscillator; not connected if external clock
signal is used
input terminal for crystal oscillator or connection of external oscillator
with CMOS compatible square wave clock signal
digital positive supply voltage for internal crystal oscillator (3.3 V)
digital supply voltage E2 (external pad supply 2; 3.3 V)
ground 2 for digital supply voltage input E (external pad supply)
test data output for boundary scan test; see
test clock input for boundary scan test; see
test data input for boundary scan test; see
test mode select input for boundary scan test or scan test; see
note 3
2
C-bus bit RTSE13 to RTSE10 (see
2
2
2
C-bus control signals MODE3 to MODE0.
C-bus control signals MODE3 to MODE0.
C-bus) with inactive output path
Table
Table
2
2
C-bus)
C-bus bit OERT.
7). If I
7). If I
Table
2
2
C-bus bit VIPB = 1, the higher bits
C-bus bit VIPB = 1, the lower bits
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
50). RTS0 is strapped during
Table
9-bit video input processor
Table note 3
51)
Table note 3
Table note 3
SAA7113H
2
C-bus slave address is
2
2
C-bus registers
C-bus registers
2
C-bus
Table
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