SAA7113H NXP Semiconductors, SAA7113H Datasheet
SAA7113H
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SAA7113H Summary of contents
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... SECAM), a brightness, contrast and saturation control circuit, a multistandard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V CMOS circuit SAA7113H, analog front-end and digital video decoder highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU-R BT 601 compatible color component values ...
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... PCMCIA card application AGP based graphics cards Image processing Video phone applications Intercast and PC teletext applications Security applications. 9397 750 14232 Product data sheet Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 2 C-bus © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Ordering information Package Name Description QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Min Typ Max Unit 3.0 3.3 3.6 V 3.1 3.3 3.5 ...
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... BOUNDARY 8 SCAN TEST TRST AND 36 TDO SCAN TEST DDDE1 DDDA V DDDI Fig 1. Block diagram of SAA7113H 9397 750 14232 Product data sheet MULTI-STANDARD DATA SLICER VBI DATA BYPASS UPSAMPLING FILTER bypass CHROMINANCE CIRCUIT C/CVBS AND BRIGHTNESS CONTRAST SATURATION CONTROL CON Y/CVBS LUMINANCE ...
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... P positive supply voltage (3.3 V) for internal Clock Generation Circuit (CGC ground for internal clock generation circuit Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 33 V DDDA 32 XTALI 31 XTAL 30 ...
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... I test data input for boundary scan test; see 39 I test mode select input for boundary scan test or scan test; see note 3 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 2 Table 7 C-bus bit VIPB = 1, the higher bits 2 C-bus control signals MODE3 to MODE0. ...
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... TDO is a 3-state output pad. 8. Functional description 8.1 Analog input processing The SAA7113H offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC (see Figure 8 ...
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... GAIN 60 1 HSY analog input level maximum range (p-p) 18/ minimum Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor TV line CLAMP HCL mgl065 controlled ADC input level 0 dB mhb325 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... CIRCUIT 4 AI11 MODE CLAMP CONTROL CONTROL HCL MODE3 MODE2 MODE1 MODE0 6 AGND LUM CHR Fig 6. Analog input processing using the SAA7113H as differential front-end with 9-bit ADC ANALOG ANTI-ALIAS BYPASS AMPLIFIER FILTER SWITCH DAC9 FUSE[1:0] ANALOG ANTI-ALIAS BYPASS AMPLIFIER FILTER SWITCH DAC9 ...
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... STOP X = system variable AGV FGV > GUDL; GUDL = gain update level (adjustable); VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor gain DAC 9 LUMA/CHROMA DECODER HOLDG ...
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... CLL NO CLAMP CLAMP CLAMP WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse. and C R Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 0 GAIN -> HSY SBOT WIPE ...
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... The resulting signals are fed to the variable Y-delay compensation and the output interface, which contains the VPO output formatter and the output control logic (see Figure 9397 750 14232 Product data sheet 10). Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Product data sheet (1) 6 (2) ( 0.54 1.08 Transfer characteristics of the chrominance low-pass dependent on CHBW[1:0] settings. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor mgd147 (4) (1) (3) (2) 1.62 2.16 2.7 f (MHz) © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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LUM CHR 8 TRST 37 TCK QUADRATURE TEST 38 DEMODULATOR TDI CONTROL 39 BLOCK TMS 36 TDO SUBCARRIER GENERATION RESET 18 V DDDE1 HUEC 29 V DDDI POWER- DDDA CONTROL 34 V DDDE2 CSTD[2:0] CE CLOCKS 16 V ...
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... C-bus subaddress 09h; see 18 Y (1) 6 (2) (4) ( different aperture band-pass center frequencies Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor = 4.43 MHz or 3.58 MHz 0 2 C-bus bit BYPS (subaddress 09h, bit 7) for Table 37) in two band-pass Figure 11 Figure 19). (1) (2) (4) (3) ...
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... Fig 13. Luminance control subaddress 09h, 4.43 MHz trap/CVBS mode, prefilter off and 9397 750 14232 Product data sheet (1) (2) (3) ( different aperture factors (1) (2) (4) ( different aperture band-pass center frequencies Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor mgd140 (4) (3) (2) ( (MHz) Y mgd141 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Fig 15. Luminance control subaddress 09h, Y/C mode, prefilter off and different aperture 9397 750 14232 Product data sheet (1) (2) (3) ( factors (1) (2) ( factors Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor mgd142 (MHz) Y mgd143 (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Product data sheet (1) (2) (4) ( different aperture band-pass center frequencies (1) (2) ( different aperture factors Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor mgd144 (1) (2) (4) ( (MHz) Y mgd145 (4) (3) (2) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Fig 18. Luminance control subaddress 09h, 3.58 MHz trap/CVBS mode, prefilter off and 9397 750 14232 Product data sheet (1) (2) ( different aperture band-pass center frequencies Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor mgd146 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... DETECTOR COARSE AUFD HSB[7:0] HSS[7:0] HPLL HTC[1:0] FIDT FSEL HLCK LOOP FILTER COUNTER RTS1 Figure 19). Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Y AND ADDING STAGE APER0 APER1 VBLB CLOCK CIRCUIT CLOCKS LINE-LOCKED CLOCK GENERATOR CLOCK DAC6 GENERATION CIRCUIT HTC[1:0] ...
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... LLC4 (internal) LLC8 (virtual) 9397 750 14232 Product data sheet f (60 Hz). H ZERO BAND PASS CROSS FC = LLC/4 DETECTION DETECTION Clock frequencies Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor f (50 Hz PHASE LOOP OSCILLATOR FILTER DIVIDER DIVIDER 1/2 Frequency (MHz) 24.576 27 13 ...
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... PLL delay CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock; RESINT = internal reset; LLC = line-locked clock output. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor supply voltages (below 2.8 V) will DDA0 Figure Table 5). POC V POC V ...
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... Supported VBI standards Data rate (Mbit/s) 6.9375 0.500 5 5 5.7272 0.503 6.9375 1.8125 1.7898 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Remarks direct switching to high-impedance for 200 ms internal reset sequence after power-on (reset sequence) a complete 2 I C-bus transmission is required ...
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... US teletext (WST) sliced US closed caption (line 21) YUV video component signal, VBI region raw oversampled CVBS data Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Framing code FC window Hamming programmable NABTS programmable (A7h) Japtext programmable ...
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... C-bus bit VBLB is set. This data type is defined for future enhancements; it could Table 46). Format and nominal levels are given in Table 34, Table 35 and Table and Table 18. 20. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor …continued Name general text VITC625 VITC625 - NABTS Japtext JFS active video Table 14) ...
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... V vertical blanking bit VBI active video for vertical timing see SAV EAV P[3:0] reserved; evaluation not recommended (protection bits according to ITU-R BT 656) 16). Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Table 9 and Table 10 Table 9 and Table 10 Figure 24). Table 9 Table 9 and ...
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... Hz vertical timing F V (ITU-R BT 656) OFTS1 = 0; OFTS0 = 0 (ITU-R BT 656 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor OFTS1 = 0; OFTS0 = 1 OFTS1 = 1; OFTS0 = 0 VRLN = 0 VRLN = according to selected data type 1 1 via LCR2 to LCR24 1 1 (subaddresses 41h to 57h): data types 14 data 0 0 type 15 ...
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Table 11: Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st ...
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Table 14: Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st ...
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... color difference component, pixel number 718 Y (luminance) component, pixel number 719 color difference component, pixel number 718 end of active video range (see Table 8 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 255 blue 100 % 240 blue 75 % 212 colorless 128 ...
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... NTSC M) Oversampled CVBS samples ... Yn Table 8 to Table 10) 9.2.8) Table 8 to Table 10) Sliced data Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 255 white 199 LUMINANCE black shoulder = black 60 SYNC 1 sync bottom b. For sources not containing black level offset Timing reference ...
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... FSC-PLL and PAL sequence bit. The signal can be used for various applications in external circuits, e. digital encoder to achieve clean encoding. The SAA7113H supports RTC level 3.1 (see external document “RTC Functional Description” , available on request). 8.12 RTS0 and RTS1 terminals ...
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... Subaddress Data LSB slave address read/write control bit order to write (the circuit is slave receiver); [1] The SAA7113H supports the ‘fast mode’ I [2] If more than one byte DATA is transmitted the subaddress pointer is automatically incremented. 9397 750 14232 Product data sheet Digital output control via RTS1 (enabled by bits RTSE1[3: ...
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... Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Access Reference R Section 9.2.1 R/W Section 9.2.2 to Section 9.2.6 R/W Section 9 ...
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Table 25: I C-bus receiver/transmitter overview Register function Subaddress D7 (hex) Chip version (read only) 00 ID07 [1] Increment delay 01 Analog input control 1 02 FUSE1 [1] Analog input control 2 03 Analog input control 3 04 GAI17 ...
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Table 25: I C-bus receiver/transmitter overview Register function Subaddress D7 (hex) AC1 40 FISET LCR2 41 LCR02_7 LCR3 to LCR23 LCRn_7 LCR24 57 LCR24_7 FC 58 FC7 HOFF 59 HOFF7 VOFF 5A VOFF7 HVOFF 5B FOFF ...
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... Y (automatic gain) from AI12 (pin (gain [ (automatic gain) from AI11 (pin (gain [ (automatic gain) from AI12 (pin (gain Figure 27 to Figure 34). Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Logic levels ID07 ID06 ID05 CV3 CV2 CV1 IDEL3 IDEL2 ...
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... CHROMA AI22 AI21 LUMA AI12 AI11 mhb347 Fig 34. Mode (gain channel 2 adapted to Y Analog control 1 subaddress 02h (D5 and D4) (see Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor AD2 AD1 AD2 AD1 AD2 AD1 2 I C-bus bit BYPS (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth) ...
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... Gain control analog (AICO3); static gain control channel 1 GAI1 subaddress 04h (D7 to D0) Gain Sign Control bits (dB) bit GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Figure 6) Control bits D7 and D6 FUSE1 Logic level see Table 32 see Table ...
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... Control bits HSS7 HSS6 HSS5 HSS4 forbidden (outside available central counter range forbidden (outside available central counter range Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor HSB3 HSB2 HSB1 HSB0 HSS3 HSS2 HSS1 HSS0 ...
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... Horizontal time constant selection (HTC1 and HTC0) TV mode (recommended for poor quality TV signals only; do not use for new applications) VTR mode (recommended if a deflection control circuit is directly connected to SAA7113H) Reserved Fast locking mode (recommended setting) Forced ODD/EVEN toggle FOET ODD/EVEN signal toggles only with interlaced source ODD/EVEN signal toggles fi ...
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... Figure 11, Figure Luminance brightness control subaddress 0Ah (D7 to D0) Control bits BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor …continued Control bit Logic level Data bit APER1 1 APER0 0 APER1 1 APER0 1 UPTCV 0 UPTCV 1 VBLB ...
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... Chrominance saturation control subaddress 0Ch (D7 to D0) Control bits SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Chrominance hue control subaddress 0Dh (D7 to D0) Control bits HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chrominance control subaddress 0Eh 60 Hz Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor ...
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... PAL 4.43 (60 Hz) NTSC 4.43 (60 Hz) PAL M reserved Chrominance gain control subaddress 0Fh (D6 to D0) Control bits CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor …continued Control bit Logic level FCTC 0 FCTC 1 DCCF 0 DCCF 1 ...
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... Fine position of HS HDEL0 and HDEL1 subaddress 10h (D5 and D4) Output format selection OFTS0 and OFTS1 subaddress 10h (D7 and D6); see Table 9 and Table 10 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Control bit D7 ACGC 0 1 YDEL1 YDEL0 ...
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... VIPB (subaddress 11h, bit LSBs of the 9-bit ADCs GPSW0 level (subaddress 11h, bit 5) 9397 750 14232 Product data sheet Output control 1 subaddress 11h 22) RTS0 output control subaddress 12h Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Bit Logic level Data bit COLO 0 D0 ...
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... VSTA0, subaddresses 15h and 17h and FIDP, subaddress 13h, bit 3) 9397 750 14232 Product data sheet RTS0 output control subaddress 12h and Table 62) Figure Figure 38 and Figure 39 39) and Figure 39) Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor …continued Control bits RTSE03 RTSE02 RTSE01 RTSE00 ...
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... VSTA0, subaddresses 15h and 17h and FIDP, subaddress 13h, bit 3) 9397 750 14232 Product data sheet RTS1 output control subaddress 12h and Table 62) Figure Figure 38 and Figure 39 and Figure 39 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Control bits RTSE13 RTSE12 RTSE11 RTSE10 Table 22 ...
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... Table 56) MSB Control bits (subaddress 17, D0) VSTA8 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Bit Logic level Data bit AOSL1 0 AOSL0 0 AOSL1 0 AOSL0 1 AOSL1 1 AOSL0 0 AOSL1 1 AOSL0 1 FIDP 0 FIDP 1 OLDSB 0 OLDSB ...
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... HIGH gain value for active luminance channel is limited [max (top)]; active HIGH identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor ...
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... HIGH = unlocked (OLDSB = 1) status bit for interlace detection; LOW = non-interlaced, HIGH = interlaced Data slicer clock selection Amplitude searching Framing code error Hamming check Field size select Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor …continued Control bits D2 and D1 CLKSEL1 CLKSEL0 ...
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... Japanese format switch programmable (L20/22) video component signal, - active video region (default) Table 63. Setting of FOFF field 1 field 2 Framing code for programmable data types Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Table [1] DT3 to DT0 0000 0001 0010 0011 0100 0101 0110 0111 ...
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... SDID codes D5 SDID5 0 Slicer status bit (subaddress 60h) read only Slicer status bit (subaddress 60h) read only Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Control bits address 59h, data bits HOFF7 to HOFF0 54h Control bits address 5Ah, data bits ...
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... Slicer status bits (subaddress 62h) read only Data type according to 2 9.3 I C-bus start setup The given values force the following behavior of the SAA7113H: • The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active • Automatic field detection enabled, PAL BDGHI or NTSC M standard expected • ...
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... OEYC, OERT, VIPB, COLO RTSE1[3:0], RTSE0[3:0] ADLSB OLDSB, FIDP, X, AOSL[1:0] VSTA[7:0] VSTO[7: VSTO8, VSTA8 INTL, HLVLN, FIDT, GLIMT, GLIMB, WIPA, COPRO, RDCAP FISET, HAM_N, FCE, HUNT_N, X, CLKSEL[1:0], X LCRn[7:0] FC[7:0] HOFF[7:0] VOFF[7:0] Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Values (binary) Start (hexadecimal ...
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... XTALI, SDA and SCL digital input voltage digital output voltage voltage difference between V and V SSA(all) SS(all) storage temperature ambient temperature electrostatic discharge voltage Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Values (binary read only read only and Table 14. ...
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... To minimize the effective R th(j-a) connected to the power and ground layers directly. An ample copper area direct under the SAA7113H with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective R solder-stop varnish under the chip ...
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... C; unless otherwise specified. amb Conditions outputs at 3-state sink current sink current DDD(max DDD(min LLC nominal frequency Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Min Typ Max [1] 0.5 - +0.3V 0.3 - +0.8 0.3 - +0.8 [2] 0. DD(I2C) DD(I2C) 2 DDD 2.0 - 5.5 - ...
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... IL(SCL,SDA)(max) 2 C-bus. For V = 3.3 V then V DD(I2C) IH(SCL,SDA)(min mA pF. Timings and levels refer to drawings and conditions illustrated OHD;DAT Typical analog delay AI22 -> ADCIN (AOUT Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Min Typ Max - 15625 - - 15734 - - - 5.7 - 4433 619 - - ...
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... Fig 36. DOT input timing (RTS1) 9397 750 14232 Product data sheet t LLC LLCH OHD;DAT t HD;DAT t SU;DAT t OHD t PDZ Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor t LLCL 2.6 V 1 2.4 V 0.6 V mhb333 t mhb334 PD © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... RTS0/1 HREF (60 Hz) 11 2/LLC 720 2/LLC RTS0/1 HS (60 Hz) RTS0/1 HS (60 Hz) 107 programming range (step size: 8/LLC) RTSE0[3: Table 79. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor burst 28 1/LLC burst 1/LLC processing delay CVBS->VPO 0 sync clipped 12 2/LLC 144 2/LLC 55 2/LLC ...
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... C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Fh. 2 C-bus bit VRLN. The luminance peaking and the chrominance trap are 2 C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 499 ...
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... C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Eh. 2 C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Fh. 2 C-bus bit VRLN. The luminance peaking and the chrominance trap are 2 C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor ...
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... Product data sheet 2 C-bus) shows a static behavior which doesn’t match the specified Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Work-around: Sometimes it will be advantageous to average the COPRO status information (under control of the system microcontroller) for about one minute. 9397 750 14232 Product data sheet Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 2 C-bus status © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... SSD SSA Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor C15 100 nF C13 V SSD 100 SAA7113H mhb349 V SSD © Koninklijke Philips Electronics N.V. 2005. All rights reserved. C14 100 nF C12 100 nF V SSD VPO7 VPO6 VPO5 VPO4 VPO3 VPO2 VPO1 ...
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... Test information 16.1 Boundary scan test The SAA7113H has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7113H follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips ...
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... Product data sheet 42). MSB TDI nnnn 0111000100010011 4-bit 16-bit part number version code Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor LSB 00000010101 11-bit manufacturer identification mhb332 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. TDO ...
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... 2.5 scale (1) ( 0.4 0.25 10.1 10.1 12.9 0.8 0.2 0.14 9.9 9.9 12.3 REFERENCES JEDEC JEITA Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Product data sheet 2 called small/thin packages. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] ...
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... Digital inputs, input leakage current: changed maximum value from 78, Digital inputs, I/O leakage current: added maximum value Product specification - Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor Doc. number Supersedes 9397 750 14232 SAA7113H_1 9397 750 04567 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Wave soldering 18.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 71 18.5 Package related soldering information . . . . . . 71 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 72 20 Data sheet status Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Rev. 02 — 9 May 2005 SAA7113H 9-bit video input processor continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands SAA7113H Date of release: 9 May 2005 Document number: 9397 750 14232 ...