GTL2008PW NXP Semiconductors, GTL2008PW Datasheet
GTL2008PW
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GTL2008PW Summary of contents
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GTL2008 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs Rev. 04 — 19 February 2010 1. General description The GTL2008 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge ...
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... Table 2. Ordering information − ° ° +85 C amb Type Topside Package number mark Name GTL2008PW GTL2008 TSSOP28 GTL2008_4 Product data sheet GTL translator with power good control and high-impedance outputs Conditions A port 3 port nBI; see Figure 4 nBI nAO (open-drain outputs); see Figure nBI ...
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... NXP Semiconductors 5. Functional diagram 1 GTL VREF 2 1AO LVTTL outputs (open-drain) 3 2AO 4 5A LVTTL inputs/outputs (open-drain LVTTL input EN1 7 GTL input 11BI LVTTL input/output 8 11A (open-drain) 9 GTL input 9BI 10 3AO LVTTL outputs (open-drain) 11 4AO 12 10AI1 LVTTL inputs 13 10AI2 (1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs ...
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... GTL2008_4 Product data sheet GTL translator with power good control and high-impedance outputs VREF 1 2 1AO 2AO EN1 6 7 11BI GTL2008PW 8 11A 9BI 9 3AO 10 4AO 11 12 10AI1 13 10AI2 GND 14 Pin configuration for TSSOP28 Pin description Pin Description 1 GTL reference voltage ...
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... NXP Semiconductors Table 3. Symbol 6BI 5BI 11BO EN2 7BO2 7BO1 2BI 1BI Functional description Refer to 7.1 Function tables Table HIGH voltage level LOW voltage level. Input 1BI/2BI/3BI/4BI/9BI L H [1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table Table 5 ...
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... NXP Semiconductors Table HIGH voltage level LOW voltage level Don’t care. Inputs 10AI1/10AI2 Table HIGH voltage level LOW voltage level. Input 5BI/6BI [1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs ...
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... NXP Semiconductors 8. Application design-in information V TT 1.5 kΩ to 1.2 kΩ PLATFORM HEALTH MANAGEMENT CPU1 1ERR_L CPU1 THRMTRIP L CPU1 PROCHOT L CPU2 PROCHOT L NMI_L CPU2 1ERR_L CPU2 THRMTRIP L CPU1 SMI L CPU2 SMI L SMI_BUFF_L SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supply POWER GOOD (1) If 9AO needs to be HIGH before EN2 goes HIGH, a pull-up resistor is required because it is high-impedance until EN2 goes HIGH ...
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... NXP Semiconductors 9. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I LOW-level output current ...
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... NXP Semiconductors 11. Static characteristics Table 12. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). T Symbol Parameter V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I input current I I supply current CC ΔI [3] additional supply CC current C input/output io capacitance [1] All typical values are measured at V [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed ...
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... NXP Semiconductors 12. Dynamic characteristics Table 13. Dynamic characteristics ± 3 Symbol Parameter 1.1 V ref TT t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL t LOW to OFF-state PLZ propagation delay t OFF-state to LOW PZL propagation delay t HIGH to OFF-state PHZ propagation delay ...
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... NXP Semiconductors Table 13. Dynamic characteristics ± 3 Symbol Parameter 1.2 V ref TT t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL t LOW to OFF-state propagation PLZ delay t OFF-state to LOW PZL propagation delay t HIGH to OFF-state PHZ propagation delay t OFF-state to HIGH ...
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... NXP Semiconductors 12.1 Waveforms 1.5 V for A port and Pulse duration Fig 4. Voltage waveforms input V ref t PLH output 1.5 V PRR ≤ 10 MHz Ω Fig 5. Propagation delay, 9BI to 9AO input V ref t PLH output V ref Fig 7. 5BI to 7BO1 or 6BI to 7BO2 GTL2008_4 Product data sheet GTL translator with power good control and high-impedance outputs ≥ ...
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... NXP Semiconductors input V ref t PLZ output Fig 9. 11BI to 11A Fig 11. EN2 to 9AO GTL2008_4 Product data sheet GTL translator with power good control and high-impedance outputs ref PZL V OH output 1 002aac196 Fig 10. 11A to 11BO input 1 PHZ PZH output All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 13. Test information Fig 12. Load circuit for A outputs (9AO) Fig 13. Load circuit for B outputs Fig 14. Load circuit for open-drain LVTTL I/O and open-drain outputs Fig 15. Load circuit for 9AO OFF-state to LOW and LOW to OFF-state R — Load resistor L C — Load capacitance; includes jig and probe capacitance ...
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... NXP Semiconductors 14. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 16. Acronym CDM CMOS CPU DUT ESD GTL HBM LVTTL MM PRR TTL VRD GTL2008_4 Product data sheet ...
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... NXP Semiconductors 17. Revision history Table 17. Revision history Document ID Release date GTL2008_4 20100219 • Modifications: Section 2 “Features and JESD22-A115” to “150 V MM per JESD22-A115” GTL2008_3 20070201 GTL2008_GTL2107_2 20060926 GTL2008_1 20060502 GTL2008_4 Product data sheet GTL translator with power good control and high-impedance outputs ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any 19. Contact information For more information, please visit: ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Application design-in information . . . . . . . . . . 7 9 Limiting values Recommended operating conditions Static characteristics ...