TDA9950TT/C2 NXP Semiconductors, TDA9950TT/C2 Datasheet - Page 4

• Manufacturer Part Number: TDA9950TT/C2
• Manufacturer: NXP Semiconductors

Specifications of TDA9950TT/C2

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: TSSOP
• Pin Count: 20
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
8. Functional description
TDA9950_2
Product data sheet
8.1 Device addressing
Table 3.
[1]
The TDA9950 uses an internal processor with embedded software to control the interface
between the CEC line and the I
The TDA9950 is a slave I
and protocol for the I
Table 4.
[1]
A1 and A0 are hardware-selectable pins.
Symbol
RST
V
XTAL1
XTAL2
CEC_IN
SDA
SCL
RSVD2
RSVD3
RSVD4
RSVD5
V
RSVD6
RSVD7
INT_POL
A1
A0
Address code
Bit
Value
SS
DD
I = input, O = output, P = power supply.
The Most Significant Bit (MSB), b7, is sent first.
Pin description
Device address code
Pin
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Device code
b7
0
[1]
2
Type
I
P
I
O
I
I/O
I
I
O
O
I
P
I
I
I
I
I
C-bus are standard.
Rev. 02 — 22 October 2009
2
[1]
b6
1
…continued
C-bus device and the SCL pin is an input pin only. The timing
Description
RST — External reset input. A LOW state on this pin resets the
translator.
Ground: 0 V reference (GND).
XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (12 MHz crystal).
XTAL2 — Output from the oscillator amplifier.
CEC_IN — Input for CEC line.
SDA — I
SCL — I
RSVD2 — Reserved pin (should be connected to ground).
RSVD3 — Reserved pin.
RSVD4 — Reserved pin.
RSVD5 — Reserved pin (should be connected to ground).
Power supply — This is the (core digital 3.3 V) power supply
voltage for normal operation as well as Idle and Power-down
modes.
RSVD6 — Reserved pin (should be connected to ground).
RSVD7 — Reserved pin (should be connected to ground).
INT_POL — Sets the polarity of the active output required on
the INT signal (pin 2). Leave floating or pull-up to V
HIGH output when active (rising edge), connect to V
LOW output when active (falling edge). This input is latched at
reset.
A1 — I
A0 — I
2
C-bus.
b5
1
2
2
C-bus slave address bit 2.
C-bus slave address bit 1.
2
2
C-bus serial clock input.
C-bus serial data input/output (open-drain).
b4
0
b3
1
Chip enable
b2
A1
CEC/I
TDA9950
© NXP B.V. 2009. All rights reserved.
2
b1
A0
C-bus translator
DD
SS
for a
for a
R/W
b0
R/W
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