MT46H64M16LFCK-5:A Micron Technology Inc, MT46H64M16LFCK-5:A Datasheet - Page 22

• Manufacturer Part Number: MT46H64M16LFCK-5:A
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H64M16LFCK-5:A

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 130mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 9: I
Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; V
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Parameter/Condition
Self refresh:
CKE = LOW;
inputs are stable; Data bus inputs are stable
DD6
t
CK =
Specifications and Conditions
t
CK (MIN); Address and control
Notes:
10. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH
12. Values for I
13. Typical values at 25˚C, not a maximum value.
1. All voltages referenced to V
2. Tests for I
3. Timing and I
4. I
5. I
6. MIN (
7. Measurement is taken 500ms after entering into this operating mode to provide settling
8. V
9. I
related specifications and device operation are guaranteed for the full voltage range
specified.
but input timing is still referenced to V
output timing reference voltage level is V
minimum cycle time with the outputs open.
aged at the defined cycle rate.
minimum absolute value for the respective parameter.
ments is the largest multiple of
time for the tester.
From the time the AUTO REFRESH command is registered, CKE must be active at each
rising clock edge until
command period (
ues are estimated.
DD
DD
DD2N
DD
is dependent on output loading and cycle rates. Specified values are obtained with
specifications are tested after the device is properly initialized and values are aver-
must not vary more than 4% if CKE is not active while any bank is active.
t
specifies DQ, DQS, and DM to be driven to a valid high or low logic level.
RC or
DD
DD6
t
characteristics may be conducted at nominal supply voltage levels, but the
DD
RFC) for I
85˚C are guaranteed for the entire temperature range. All other I
tests may use a V
t
RFC [MIN]) else CKE is LOW (for example, during standby).
1/16 array, 85˚C
1/16 array, 45˚C
Full array, 85˚C
Full array, 45˚C
1/2 array, 85˚C
1/2 array, 45˚C
1/4 array, 85˚C
1/4 array, 45˚C
1/8 array, 85˚C
1/8 array, 45˚C
DD
t
RFC later.
measurements is the smallest multiple of
22
SS
Electrical Specifications – I
.
t
CK that meets the maximum absolute value for
IL
-to-V
1Gb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
IH
DDQ
DD
Symbol
swing of up to 1.5V in the test environment,
DDQ
/V
I
/2 (or to the crossing point for CK/CK#). The
DD6
DDQ
/2.
= 1.70–1.95V
Low Power
1000
500
750
440
600
380
550
350
500
330
t
RAS (MAX) for I
© 2007 Micron Technology, Inc. All rights reserved.
Standard
t
CK that meets the
DD
1200
750
900
730
750
680
750
620
700
540
DD
Parameters
measure-
t
DD6
Units
RAS.
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
val-