TEA5768HL/V2 STEricsson, TEA5768HL/V2 Datasheet - Page 19

• Manufacturer Part Number: TEA5768HL/V2
• Manufacturer: STEricsson

Specifications of TEA5768HL/V2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 14.
Table 15.
[1]
SAA7133HL_2
Product data sheet
DMA
1
2
3
4
DMA
1
2
3
4
Active video, unscaled YUV 4 : 2 : 2.
Data stream
Y
U
V
audio
Data stream
raw VBI
-
MPEG stream
audio
FIFO configuration: typical example
FIFO configuration: fastidious example
6.4.4 Virtual and physical addressing
[1]
Most operating systems allocate memory to requesting applications for DMA as
continuous ranges in virtual address space. The data flow over the PCI-bus points to
physical addresses, usually not continuous and split in pages of 4 kB (Intel architecture,
most UNIX systems, Power PC).
The association between the virtual (logic) address space and the fragmented physical
address space is defined in page tables (system files); see
incorporates hardware support (MMU) to translate virtual to physical addresses on the fly,
by investigating the related page table information. This hardware support reduces the
demand for real-time software interaction and interrupt requests, and therefore saves
system resources.
Data rate
13.5 MB/s
6.75 MB/s
6.75 MB/s
160 kB/s
Data rate
27 MB/s
-
9.5 Mbit/s
192 kB/s
Rev. 02 — 18 February 2008
FIFO size programmable to
640 B
-
256 B
128 B
FIFO size programmable to
384 B
256 B
256 B
128 B
PCI audio and video broadcast decoder
Tolerant to latency of
22.5 s
-
202.1 s
583.3 s
Figure
Tolerant to latency of
28.4 s
37.9 s
37.9 s
800 s
SAA7133HL
7. The SAA7133HL
© NXP B.V. 2008. All rights reserved.
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