LFXP3E-3TN100C LATTICE SEMICONDUCTOR, LFXP3E-3TN100C Datasheet - Page 22

• Manufacturer Part Number: LFXP3E-3TN100C
• Description: FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.2V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP3E-3TN100C

• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 2-23. Output Register Block
Figure 2-24. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Routing
From
ONEG0
OPOS0
CLK1
*Latch is transparent when input is low.
CLK
LSR
DA
DB
/LATCH
D
D
D-Type
LATCH
LE*
ODDRXB
2-19
Q
Q
Q
0
1
Programmed
Control
LatticeXP Family Data Sheet
OUTDDN
0
1
To sysIO
Buffer
DO
Architecture