LFXP3E-3TN100I Lattice, LFXP3E-3TN100I Datasheet
LFXP3E-3TN100I
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LFXP3E-3TN100I Summary of contents
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... LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back- annotates it into the design for timing verification. ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Functional Unit (PFU) PFU and PFF Blocks The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... Different slice / PFU Fast Carry In (FCI) Slice CO F LUT4 & SUM CARRY CI LUT Expansion Mux CO LUT4 & F CARRY OFX0 SUM From Different slice / PFU Fast Carry Out (FCO) 2-3 Architecture LatticeXP Family Data Sheet OFX1 F1 D FF/ Q1 Latch To Routing OFX0 F0 D FF/ Q0 Latch ...
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... Output of a LUT6, LUT7, LUT8 FCO For the right most PFU the fast carry chain output Logic Ripple 2-bit Arithmetic Unit 2-bit Arithmetic Unit 2-4 Architecture LatticeXP Family Data Sheet Description 2 MUX depending on the slice 1 RAM ROM SP 16x2 ROM 16x1 x 2 N/A ...
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... Lattice Semiconductor The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis- tributed memory primitive block diagrams ...
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... MUX 16x1 These modes are not available in PFF blocks Routing There are many resources provided in the LatticeXP devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). ...
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... Note: Smaller devices have two PLLs. Secondary Clock Sources LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6 ...
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... From Routing Clock Routing The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net- work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2- 8 ...
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... VCO to operate at higher frequencies than the clock output, thereby increasing the fre- quency range. The secondary divider is used to derive lower frequency outputs. 4 Secondary Clocks per Quadrant Routing GND parameter has been satisfied. Additionally, the phase and duty cycle block LOCK 2-9 Architecture LatticeXP Family Data Sheet Clock to Each Slice ...
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... Controlled VCO Adjust Oscillator Divider (CLKFB) RST CLKOP CLKI LOCK CLKFB DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] Description 2-10 Architecture LatticeXP Family Data Sheet LOCK Post Scalar Phase/Duty CLKOS Divider Select (CLKOP) CLKOP Secondary Clock CLKOK Divider (CLKOK) CLKOP CLKOS CLKOK LOCK ...
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... SEL DCSOUT sysMEM Memory The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6 ...
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... ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-14 shows the four basic memory confi ...
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... EBR RSTA WEA CSA[2:0] DOA[17:0] True Dual Port RAM ADW[12:0] DI[35:0] CLKW CEW DO[35:0] EBR WE RST CS[2:0] ROM Pseudo-Dual Port RAM 2-13 Architecture LatticeXP Family Data Sheet ADB[12:0] DIB[17:0] CEB CLKB EBR RSTB WEB CSB[2:0] DOB[17:0] ADR[12:0] DO[35:0] EBR CER CLKR ...
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... Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO buffer, and receives input from the buffer. Memory Core Output Data Programmable Disable Reset Clock Clock Enable 2-14 Architecture LatticeXP Family Data Sheet SET Q Port A[17: CLR Latches SET Port B[17:0] Q ...
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... DQS DDRCLKPOL In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential pairs, one PIC pair and one single I/O, as shown in Figure 2-18. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”). The PAD Labels “T” and “ ...
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... Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and LatticeXP Family Data Sheet PIO A PADA “T” ...
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... DDR memory section of this data sheet. Figure 2-20. Input Register Diagram DI (From sysIO Buffer) Delay Block Fixed Delay DQS Delayed (From DQS Bus) CLK0 (From Routing) DDRCLKPOL (From DDR Polarity Control Bus) LatticeXP Family Data Sheet SDR & Sync DDR Registers Registers D-Type D-Type /LATCH ...
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... Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available. The additional register for DDR operation does not have reset or clock enable available ECLK QA LSR IDDRXB SCLK QB CE DDRCLKPOL 2-18 Architecture LatticeXP Family Data Sheet ...
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... In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0 D-Type /LATCH Q D LATCH LE* *Latch is transparent when input is low ODDRXB CLK LSR 2-19 Architecture LatticeXP Family Data Sheet OUTDDN sysIO 1 Buffer Programmed Control Q ...
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... Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input (for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeXP devices provide this capability. In addition to these registers, the LatticeXP devices contain two elements to simplify the design of input structures for read operations: the DQS delay block and polarity control logic ...
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... Reg. GSR CLKI CEI To DDR DQS Reg. PIO Polarity Control Logic DQSDEL Calibration Bus from DLL Polarity Control Signal Bus DLL DLL 2-21 Architecture LatticeXP Family Data Sheet DDR sysIO Datain Buffer PAD DI DQS sysIO Strobe Buffer PAD DI DQS Signal Bus ...
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... Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer- enced input buffers. In the LatticeXP devices, a dedicated pin in a bank can be configured reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages. ...
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... GND Note: N and M are the maximum number of I/Os per bank. LatticeXP devices contain two types of sysIO buffer pairs. 1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only) The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be confi ...
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... LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet ...
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... Emulated with external resistors. Hot Socketing The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and power- down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specifi ...
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... Device Configuration All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide and serial confi ...
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... Oscillator Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for configura- tion. The oscillator and the master serial clock run continuously in the configuration mode. The default value of the LatticeXP Family Data Sheet ...
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... Table 2-10. Selectable Master Serial Clock (CCLK) Frequencies During Configuration Density Shifting The LatticeXP family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases also possible to shift a lower utilization design tar- geted for a high-density device to a lower density device. However, the exact details of the fi ...
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... CCAUX © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... CCIO CCIO additive PU LVCMOS and LVTTL only Condition 0 ≤ V ≤ V (MAX and V . However, assumes monotonic rise/fall rates for V CCIO (MAX). CCAUX 3-2 DC and Switching Characteristics LatticeXP Family Data Sheet Min. Typ. Max. — — +/-1000 V and V CC, CCAUX CCIO. Units µA ...
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... LFXP20C All LFXP ‘C’ Devices LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3C LFXP6C 5 LFXP10C LFXP15C LFXP20C All LFXP ‘C’ Devices 3-3 DC and Switching Characteristics LatticeXP Family Data Sheet Min. Typ. Max. — — 10 — — 40 -30 — -150 30 — 150 30 — ...
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... A 6. Per bank Over Recommended Operating Conditions Device LFXP3E LFXP6E LFXP10E LFXP15E LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C All LFXP3E/C LFXP6E/C LFXP10E/C LFXP15E/C LFXP20E/C 6 All All 3-4 DC and Switching Characteristics LatticeXP Family Data Sheet 5 Typ. Units ...
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... Assume normal bypass capacitor/decoupling capacitor across the supply =25°C, power supplies at nominal voltage Over Recommended Operating Conditions Device LFXP3E LFXP6E LFXP10E LFXP15E LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3E /C LFXP6E /C LFXP10E /C LFXP15E /C LFXP20E /C All 3-5 DC and Switching Characteristics LatticeXP Family Data Sheet 7 Typ. Units 110 ...
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... JTAG programming is at 1MHz =25°C, power supplies at nominal voltage When programming via JTAG. DC and Switching Characteristics Device LFXP3E LFXP6E LFXP10E LFXP15E LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3E /C LFXP6E /C LFXP10E /C LFXP15E /C LFXP20E /C 7 All 3-6 LatticeXP Family Data Sheet .6 Typ Units ...
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... HSTL 18 Class I, II 1.71 HSTL 18 Class III 1.71 LVDS 2.375 1 LVPECL 3.135 1 BLVDS 2.375 1. Inputs on chip. Outputs are implemented with the addition of external resistors. DC and Switching Characteristics LatticeXP Family Data Sheet V CCIO Typ. Max. Min. 3.3 3.465 — 2.5 2.625 — 1.8 1.89 — ...
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... REF V + 0.1 3.6 0.4 REF V + 0.1 3.6 0.4 REF V + 0.1 3.6 0.4 REF V + 0.1 3.6 0.4 REF 3-8 DC and Switching Characteristics LatticeXP Family Data Sheet V Min (V) (mA) (mA) 20, 16, 12, -20, -16, -12 0.4 CCIO 0.2 0.1 CCIO 20, 16, 12, -20, -16, -12 0.4 ...
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... 100 ohms 100 ohms )/ 100 ohms Driver outputs OD shorted 3-9 DC and Switching Characteristics LatticeXP Family Data Sheet Min. Typ. Max. 0 — 2.4 +/-100 — — 1.2 1.8 THD V /2 1.2 1.9 THD V /2 1.2 2.0 THD — — +/-10 — 1.38 1 ...
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... I and class II) are supported in this mode. LVDS25E The top and bottom side of LatticeXP devices support LVDS outputs via emulated complementary LVCMOS out- puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi- ble solution for point-to-point signals ...
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... Over Recommended Operating Conditions Description Output impedance Left end termination Right end termination Output high voltage Output low voltage Output differential voltage Output common mode voltage DC output current 3-11 DC and Switching Characteristics LatticeXP Family Data Sheet 2.5V 45-90 ohms 80 2. 2.5V Typical Units ...
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... RSDS The LatticeXP devices support differential RSDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Output impedance Driver series resistor Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current 3-13 DC and Switching Characteristics LatticeXP Family Data Sheet + Off-chip Typical Units 20 ohms 300 ohms ...
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... These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v.F0.11 DC and Switching Characteristics LatticeXP Family Data Sheet 1 -5 Timing 6.1 7 ...
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... Logic timing provided in the following sections of this data sheet and in the ispLEVER design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process can be much better than the values given in the tables. The ispLEVER design tool from Lattice can provide logic timing numbers at a particular temperature and voltage. ...
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... LFXP15 LFXP20 LFXP3 LFXP6 LFXP10 LFXP15 LFXP20 All All All All All All All All LFXP3/6/10/15 LFXP20 3-16 DC and Switching Characteristics LatticeXP Family Data Sheet - Min. Max. Min. Max. Min. — 5.12 — 6.12 — — 5.30 — 6.34 — — ...
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... Lattice Semiconductor Figure 3-5. DDR Timings DQ and DQS Read Timings DQS DQ DQ and DQS Write Timings DQS DQ DC and Switching Characteristics LatticeXP Family Data Sheet t DVADQ t DVEDQ t DQVBS t DQVAS 3-17 ...
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... DC and Switching Characteristics LatticeXP Family Data Sheet - Max. Min. Max. Min. Max. 0.28 — 0.34 — 0.40 0.44 — 0.53 — 0.63 0.90 — ...
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... Reset Signal Setup Time RSTSU 1. Internal parameters are characterized but not tested on every device. Timing v.F0.11 1 (Continued) Over Recommended Operating Conditions Description Min. — 1.00 1.00 3-19 DC and Switching Characteristics LatticeXP Family Data Sheet - Max. Min. Max. Min. Max. 1.61 — 1.94 — 2.32 — ...
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... Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] DO[1:0] CK WRE AD AD[3:0] D DI[1:0] DO[1:0] Old Data Old Data 3-20 DC and Switching Characteristics LatticeXP Family Data Sheet ...
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... Figure 3-9. Read Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA Mem(n) data from previous read DOA (Registered DOA Mem(n) data from previous read output is only updated during a read cycle 3-21 DC and Switching Characteristics LatticeXP Family Data Sheet ACCESS ACCESS ACCESS ACCESS D1 D0 ...
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... Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock ACCESS ACCESS ACCESS old A0 Data old A1 Data Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-22 DC and Switching Characteristics LatticeXP Family Data Sheet ACCESS ACCESS ACCESS ...
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... DC and Switching Characteristics LatticeXP Family Data Sheet -4 -3 Units 0.5 0.5 0.4 0.4 0.5 0.5 0.6 0.6 0.4 0.4 0.4 0.4 0.4 0.4 0.4 ...
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... DC and Switching Characteristics LatticeXP Family Data Sheet -4 -3 Units 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.1 0.1 0.3 0.3 0.1 0.1 0.3 ...
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... Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after t for PLL reset and dynamic delay adjustment. LOCK 3. Using LVDS output buffers compared to CLKOP output. Timing v.F0.11 LatticeXP “C” Sleep Mode Timing Parameter t SLEEPN Low to I/O Tristate PWRDN t SLEEPN High to Power Up ...
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... Lattice Semiconductor LatticeXP sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t Clock to Dout in Flowthrough Mode CODO t CS[0:1] Setup Time to CCLK SUCS t CS[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
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... BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN BUTCO 3-27 DC and Switching Characteristics LatticeXP Family Data Sheet Typ. Max. — 1.1 1.7 — 1.4 2.0 — 0.9 1.5 — 1.1 1.7 — 1.3 1.9 Min. Max. — — 20 — 20 — ...
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... Note: Output test conditions for all other interfaces are determined by the respective standards DUT Test Poi ∞ 0pF 188 0pF 3-28 DC and Switching Characteristics LatticeXP Family Data Sheet Timing Ref. V LVCMOS 3.3 = 1.5V — LVCMOS 2 — CCIO LVCMOS 1 — CCIO LVCMOS 1 — CCIO LVCMOS 1 ...
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... PCLK[T, C]_[n:0]_[3:0] [LOC]DQS[num] © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... V is recommended. CC Test Output Enable tri-states all I/O pins when driven low. This pin has a I weak internal pull-up, but when not used an external pull- mended. 4-2 Pinout Information LatticeXP Family Data Sheet Descriptions is recom- CC ...
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... A B Complement A B Complement A B Complement A B Complement A B Complement A B Complement A B Complement 4-3 Pinout Information LatticeXP Family Data Sheet DDR Strobe (DQS) and Data (DQ) Pins True DQ DQ True DQ DQ True DQ DQ True DQ DQ True [Edge]DQSn DQ True DQ DQ True DQ DQ ...
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... XP3 100 TQFP 144 TQFP 208 PQFP 144 TQFP 208 PQFP 256 fpBGA 62 100 8/2 12/3 9/0 12/2 8/3 12/5 6/2 13/5 5/2 14/6 12/4 12/4 4/2 13/5 10/4 12 4-4 Pinout Information LatticeXP Family Data Sheet XP6 136 100 142 20/8 ...
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... Pinout Information LatticeXP Family Data Sheet XP20 300 188 268 128 76 112 40/17 26/11 39/16 40/17 26/11 ...
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... K9, K10, L6, L11, T1, T16 XP3: 27, 33, 34, — 129, 133, 134 or GND. CC 4-6 Pinout Information LatticeXP Family Data Sheet 388 fpBGA 484 fpBGA H9, J8, J15, K8, F10, F13, G9, G10, K15, L8, L15, M8, G13, G14, H8, M15, N8, N15, P8, H15, J7, J16, K6, P15, R9 K7, K16, K17, N6, ...
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... VCC 29 PB2B 30 PB5B 31 PB8A 32 PB8B 33 GNDIO5 34 PB9A 35 PB10B 36 PB11A 37 PB11B 38 VCCIO5 39 PB12A 40 PB12B 41 PB13A 42 PB13B 43 GND Bank /TOE - 4-7 Pinout Information LatticeXP Family Data Sheet Differential Dual Function - - - - - - - - T LUM0_PLLT_FB_A C LUM0_PLLC_FB_A - - - VREF1_7 - VREF2_7 - - 3 T DQS LUM0_PLLT_IN_A C LUM0_PLLC_IN_A PCLKT6_0 C PCLKC6_0 - - - - VREF1_5 - VREF2_5 DQS ...
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... PR18A 54 PR15B 55 PR14A 56 PR13B 57 PR13A 58 VCCIO3 59 GNDP1 60 VCCP1 61 PR9B 62 PR9A 63 PR8B 64 PR8A 65 VCCIO2 66 PR6B 67 PR5A 68 GNDIO2 69 PR3B 70 PR3A 71 VCCAUX 72 TDO 73 VCCJ 74 TDI 75 TMS 76 TCK 77 VCC 78 PT24A 79 PT23A 80 PT22B 81 PT21A 82 VCCIO1 83 PT20B 84 GNDIO1 85 PT17A 86 PT16A 87 PT15B LatticeXP Family Data Sheet Bank Differential ...
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... Pin Number Pin Function 88 PT14B 89 PT13B 90 GNDIO0 91 PT13A 92 PT12B 93 PT12A 94 VCCIO0 95 PT9A 96 PT8A 97 PT6A 98 PT5A 99 GND 100 CFG0 1. Applies to LFXP “C” only. 2. Applies to LFXP “E” only. 3. Supports dedicated LVDS outputs. LatticeXP Family Data Sheet Bank Differential 4-9 Pinout Information ...
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... PL23B 3 T DQS PL24A PL24B - - PL25A PL26A PL26B - - VCCAUX - - SLEEPN - - INITN - - VCC - VREF1_5 PB5B - VREF2_5 PB8B T - PB10A C - PB10B - - GNDIO5 - - PB12A - - PB13B 4-10 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function LUM0_PLLT_FB_A 7 C LUM0_PLLC_FB_A VREF1_7 7 - VREF2_7 LUM0_PLLT_IN_A 7 C LUM0_PLLC_IN_A ...
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... GNDIO3 PR26A C - PR25B T - PR25A PR24B 3 T DQS PR24A - VREF1_3 PR23B - VREF2_3 PR22A C - PR21B T - PR21A - - GND - - PR20A C - PR19B - - VCCIO3 T - PR19A - - GNDP1 - - VCCP1 C PCLKC2_0 PR12B 4-11 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function 5 T DQS PCLKT4_0 4 C PCLKC4_0 DQS 4 ...
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... GND C BUSY PT16B T CS1N PT16A C PCLKC0_0 PT15B T PCLKT0_0 PT15A C - PT14B - - VCCIO0 T DQS PT14A - DOUT PT12A - - GNDIO0 - WRITEN PT11A - VREF1_0 PT10A 4-12 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function 2 T PCLKT2_0 2 C RUM0_PLLC_IN_A 2 T RUM0_PLLT_IN_A DQS VREF1_2 2 - VREF2_2 ...
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... Applies to LFXP “C” only. 2. Applies to LFXP “E” only. 3. Supports dedicated LVDS outputs. Dual Function Pin Function - DI PT9A - CSN PT8A - VREF2_0 PT6B - - CFG0 - - CFG1 - - DONE 4-13 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function CSN 0 - VREF2_0 ...
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... PL16A PL16B T PCLKT6_0 PL17A C PCLKC6_0 PL17B - - PL18A - - PL18B - - VCC PL21A PL21B - - GNDIO6 - VREF1_6 PL22A - VREF2_6 PL23B - - VCCIO6 3 T DQS PL24A PL24B T - PL25A C - PL25B PL26A 4-14 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function LUM0_PLLT_FB_A 7 C LUM0_PLLC_FB_A VREF1_7 7 - VREF2_7 ...
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... PB13B T DQS PB14A C - PB14B - - VCCIO5 T - PB15A C - PB15B T - PB16A C - PB16B - - GND - - VCC T - PB17A - - GNDIO4 C - PB17B T PCLKT4_0 PB18A C PCLKC4_0 PB18B T - PB19A - - VCCIO4 C - PB19B - - PB20A - - PB21B T DQS PB22A - - GNDIO4 4-15 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function /TOE - - VREF1_5 VREF2_5 ...
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... PR21B T - PR21A - - GND C - PR20B T - PR20A C - PR19B - - VCCIO3 T - PR19A - - GNDP1 - - VCCP1 - - PR13A - - GND C PCLKC2_0 PR12B T PCLKT2_0 PR12A - - PR11B - - PR11A - - GNDIO2 C RUM0_PLLC_IN_A PR8B T RUM0_PLLT_IN_A PR8A PR7B 4-16 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function 4 C VREF1_4 VREF2_4 4 T DQS ...
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... VCCIO1 C D3 PT23B T - PT23A C - PT22B T DQS PT22A - - GNDIO1 - - PT21B - D4 PT20A C - PT19B T D5 PT19A - - VCCIO1 C D6 PT18B T - PT18A - D7 PT17B - - GND - - VCC C BUSY PT16B - - GNDIO0 4-17 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function DQS VREF1_2 2 - VREF2_2 RUM0_PLLC_FB_A 2 T RUM0_PLLT_FB_A ...
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... WRITEN PT11A C - PT10B T VREF1_0 PT10A C - PT9B - - VCCIO0 T DI PT9A C - PT8B T CSN PT8A C - PT7B T - PT7A - VREF2_0 PT6B - - PT5B - - GND - - CFG0 4-18 Pinout Information LatticeXP Family Data Sheet LFXP6 Bank Differential Dual Function 0 T CS1N 0 C PCLKC0_0 0 T PCLKT0_0 DQS DOUT WRITEN VREF1_0 ...
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... PL16B PL18A PL18B - - VCCP0 - - GNDP0 T PCLKT6_0 PL20A C PCLKC6_0 PL20B - - GNDIO6 - - PL22A - VREF1_6 PL23B PL24A PL24B PL25A PL25B PL26A - - GNDIO6 PL26B PL28A 4-19 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function LUM0_PLLT_FB_A 7 C LUM0_PLLC_FB_A VREF1_7 DQS LUM0_PLLT_IN_A 7 C LUM0_PLLC_IN_A ...
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... PB10A C - PB10B T - PB11A C - PB11B - - GNDIO5 T - PB12A C VREF2_5 PB12B T - PB13A C - PB13B T - PB14A C - PB14B T - PB15A C - PB15B - - GNDIO5 - - PB16A - - PB17B T DQS PB18A C - PB18B T - PB19A C - PB19B 4-20 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function VREF2_6 DQS LLM0_PLLT_FB_A 6 C LLM0_PLLC_FB_A /TOE - - VREF1_5 ...
Page 80
... VREF2_4 PB31A C - PB31B - - PB32A - - PB33B T DQS PB34A C - PB34B T - PB35A - - GNDIO4 C - PB35B - - GNDIO3 PR34B PR34A PR33B 3 T DQS PR33A - - PR32B - VREF1_3 PR31A - - GNDIO3 C - PR29B T - PR29A 4-21 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function PCLKT4_0 4 C PCLKC4_0 DQS VREF1_4 ...
Page 81
... PR13B PR13A C RUM0_PLLC_IN_A PR12B T RUM0_PLLT_IN_A PR12A PR11B - - GNDIO2 PR8B PR8A PR7B 3 T DQS PR7A - - PR6B - VREF2_2 PR5A - - GNDIO2 PR4B PR4A C RUM0_PLLC_FB_A PR3B T RUM0_PLLT_FB_A PR3A 4-22 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A DQS VREF2_3 ...
Page 82
... DQS PT26A - - GNDIO1 - - PT25B - D4 PT24A C - PT23B T D5 PT23A C D6 PT22B T - PT22A C D7 PT21B T - PT21A C BUSY PT20B - - GNDIO0 T CS1N PT20A C PCLKC0_0 PT19B T PCLKT0_0 PT19A C - PT18B T DQS PT18A 4-23 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function - - - - - - - - - - - - - - - VREF1_1 1 T DQS ...
Page 83
... GNDIO0 T - PT6A - - CFG0 - - CFG1 - - DONE - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND 4-24 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function DOUT WRITEN VREF1_0 CSN VREF2_0 0 T DQS ...
Page 84
... VCCIO2 - - VCCIO2 - - VCCIO3 - - VCCIO3 - - VCCIO4 - - VCCIO4 - - VCCIO5 - - VCCIO5 - - VCCIO6 - - VCCIO6 - - VCCIO7 - - VCCIO7 4-25 Pinout Information LatticeXP Family Data Sheet LFXP10 Dual Bank Differential Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ...
Page 85
... PL20B PL22A PL22B - - VCCP0 - - GNDP0 T PCLKT6_0 PL28A - - GNDIO6 C PCLKC6_0 PL28B - - PL30A - VREF1_6 PL31B 3 T DQS PL32A PL32B - - GNDIO6 T LLM0_PLLT_IN_A PL33A C LLM0_PLLC_IN_A PL33B PL34A PL34B 4-26 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function LUM0_PLLT_FB_A 7 C LUM0_PLLC_FB_A VREF1_7 DQS ...
Page 86
... GNDIO5 C - PB16B - - PB17A - - PB18B T DQS PB19A C - PB19B T - PB20A C - PB20B T - PB21A C VREF2_5 PB21B T - PB22A - - GNDIO5 C - PB22B T - PB23A C - PB23B T - PB24A C - PB24B - - PB25A - - PB26B T DQS PB27A 4-27 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function VREF2_6 DQS LLM0_PLLT_FB_A 6 C LLM0_PLLC_FB_A /TOE - - ...
Page 87
... PB38B T - PB39A C - PB39B T VREF2_4 PB40A C - PB40B - - PB41A - - PB42B - - GNDIO4 T DQS PB43A C - PB43B T - PB44A C - PB44B - - GNDIO4 - - GNDIO4 - - GNDIO4 - - GNDIO3 - - GNDIO3 C RLM0_PLLC_FB_A PR42B T RLM0_PLLT_FB_A PR42A 4-28 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function PCLKT4_0 4 C PCLKC4_0 DQS 4 C VREF1_4 4 ...
Page 88
... PCLKT2_0 PR21A PR20B 3 T DQS PR20A - - PR19B - VREF1_2 PR18A - - GNDIO2 PR17B PR17A C RUM0_PLLC_IN_A PR16B T RUM0_PLLT_IN_A PR16A - - PR15B - - GNDIO2 C - PR12B T - PR12A PR11B 3 T DQS PR11A 4-29 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function DQS VREF1_3 RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A ...
Page 89
... PT39B T D0 PT39A C D1 PT38B T VREF2_1 PT38A C - PT37B T D2 PT37A - - GNDIO1 C D3 PT36B T - PT36A C - PT35B T DQS PT35A - - PT34B - D4 PT33A C - PT32B T D5 PT32A - - GNDIO1 C D6 PT31B 4-30 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function VREF2_2 RUM0_PLLC_FB_A 2 T RUM0_PLLT_FB_A ...
Page 90
... DQS PT19A - - PT18B - - PT17A - - GNDIO0 C - PT16B T - PT16A C - PT15B T - PT15A - - GNDIO0 - - GNDIO0 - - GNDIO0 - - CFG0 - - CFG1 - - DONE - - GND - - GND - - GND - - GND 4-31 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function BUSY CS1N 0 C PCLKC0_0 0 T PCLKT0_0 DQS DOUT WRITEN VREF1_0 ...
Page 91
... VCCAUX - - VCCAUX - - VCCIO0 - - VCCIO0 - - VCCIO1 - - VCCIO1 - - VCCIO2 - - VCCIO2 - - VCCIO3 - - VCCIO3 - - VCCIO4 - - VCCIO4 4-32 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ...
Page 92
... G6 VCCIO7 7 H6 VCCIO7 7 1. Applies to LFXP “C” only. 2. Applies to LFXP “E” only. 3. Supports dedicated LVDS outputs. Dual Ball Function Function - - VCCIO5 - - VCCIO5 - - VCCIO6 - - VCCIO6 - - VCCIO7 - - VCCIO7 4-33 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function ...
Page 93
... PL23A PL23B 6 C PL24A GNDIO6 6 - PL24B PL25A PL25B PL26A 6 - PL27B DQS PL28A PL28B GNDIO6 6 - 4-34 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. - PROGRAMN CCLK GNDIO7 PL6A PL6B GNDIO7 7 - PL7A 7 T PL7B 7 C LUM0_PLLC_FB_A 3 - PL8A PL8B PL9A 7 - VREF1_7 ...
Page 94
... PB10A PB10B PB11A PB11B 5 C PB12A GNDIO5 PB12B PB13A PB14B 5 - DQS PB15A PB15B PB16A 5 T 4-35 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. PL33A 6 T LLM0_PLLT_IN_A PL33B 6 C LLM0_PLLC_IN_A 3 - PL34A PL34B PL36A PL36B GNDIO6 PL37A PL37B PL38A ...
Page 95
... C - PB35A PB35B 4 C PB36A PB36B PB37A PB38B GNDIO4 4 - DQS PB39A PB39B PB40A PB40B PB41A 4 T 4-36 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. - PB20B PB21A 5 T VREF2_5 PB21B PB22A GNDIO5 PB22B PB23A PB23B PB24A PB24B PB25A PB26B ...
Page 96
... GNDIO3 PR28B DQS PR28A PR27B 3 - PR26A PR25B PR25A PR24B PR24A GNDIO3 PR23B PR23A GNDP1 - - 4-37 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. - PB45B PB46A PB46B PB47A PB47B GNDIO4 PB48A PB48B PB49A PB50B 4 - DQS PB51A PB51B PB52A GNDIO4 ...
Page 97
... TMS - - - TCK - - GNDIO1 PT48A PT47B PT47A PT46B PT45A PT44B PT44A PT43B GNDIO1 1 - 4-38 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. - VCCP1 - - - GNDIO2 PR22B PR22A 2 T PCLKC2_0 PR21B 2 C PCLKT2_0 PR21A PR20B DQS PR20A PR19B 2 - VREF1_2 PR18A ...
Page 98
... PT24A PT23B 0 C DQS PT23A PT22B 0 - DOUT PT21A PT20B GNDIO0 0 - PT20A PT19B 0 C PT19A PT18B 0 C 4-39 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. - PT47A PT46B PT46A PT45B PT45A PT44B PT44A 1 T VREF1_1 PT43B GNDIO1 1 - DQS PT43A ...
Page 99
... GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - 4-40 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. DI PT22A PT21B 0 C CSN PT21A PT20B PT20A 0 T VREF2_0 PT19B 0 C DQS PT19A PT18B PT17A GNDIO0 PT16B ...
Page 100
... VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCC - - - VCCAUX - - 4-41 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. Dual Function - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - GND - - - ...
Page 101
... VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 7 - 4-42 Pinout Information LatticeXP Family Data Sheet LFXP20 Ball Function Bank Diff. Dual Function - VCCAUX - - - VCCAUX - - - VCCAUX - - - VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 ...
Page 102
... PL12A C - PL12B PL13A PL13B PL15A PL15B - - GNDIO7 T LUM0_PLLT_IN_A PL16A C LUM0_PLLC_IN_A PL16B PL17A PL17B - VREF2_7 PL18A - - PL19B 3 T DQS PL20A - - GNDIO7 PL20B T - PL21A C - PL21B PL22A PL22B 4-43 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function LUM0_PLLT_FB_A 7 C LUM0_PLLC_FB_A VREF1_7 ...
Page 103
... PL34A PL34B PL36A PL36B - - GNDIO6 T - PL37A C - PL37B PL38A PL38B - VREF2_6 PL39A - - PL40B 3 T DQS PL41A PL41B - - GNDIO6 T LLM0_PLLT_FB_A PL42A C LLM0_PLLC_FB_A PL42B PL43A PL43B PL44A PL44B 4-44 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function PCLKT6_0 PCLKC6_0 VREF1_6 DQS ...
Page 104
... PB6B T - PB7A C - PB7B T - PB8A C - PB8B - - PB9A - - PB10B T DQS PB11A C - PB11B T - PB12A - - GNDIO5 C - PB12B T - PB13A C - PB13B T - PB14A C - PB14B T - PB15A C - PB15B T VREF1_5 PB16A - - GNDIO5 C - PB16B - - PB17A - - PB18B T DQS PB19A C - PB19B 4-45 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function DQS ...
Page 105
... PB30A C - PB30B T PCLKT4_0 PB31A C PCLKC4_0 PB31B - - GNDIO4 T - PB32A C - PB32B - - PB33A - - PB34B T DQS PB35A C VREF1_4 PB35B T - PB36A C - PB36B T - PB37A - - GNDIO4 C - PB37B T - PB38A C - PB38B T - PB39A C - PB39B T VREF2_4 PB40A C - PB40B 4-46 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function VREF2_5 DQS ...
Page 106
... PB50B T DQS PB51A C - PB51B T - PB52A C - PB52B - - GNDIO4 - - PB53A - - PB53B - - PB54A - - PB54B - - PB55A - - PB55B - - GNDIO4 - - PB56A - - GNDIO3 - - PR47A PR46B PR46A C - PR45B T - PR45A PR44B PR44A PR43B PR43A - - GNDIO3 4-47 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function DQS DQS ...
Page 107
... T - PR29A C - PR28B T - PR28A - - GNDIO3 PR27B PR27A - - PR26B - - PR26A - - PR25B - - GNDP1 - - VCCP1 - - PR24A PR23B PR23A - - GNDIO2 - - PR22B - - PR22A C PCLKC2_0 PR21B T PCLKT2_0 PR21A 4-48 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function 3 C RLM0_PLLC_FB_A 3 T RLM0_PLLT_FB_A DQS VREF1_3 RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A ...
Page 108
... PR8B PR8A C RUM0_PLLC_FB_A PR7B T RUM0_PLLT_FB_A PR7A PR6B PR6A PR5B PR5A C - PR4B T - PR4A - - GNDIO2 PR3B PR3A - - PR2B - - TDO - - VCCJ - - TDI - - TMS - - TCK - - PT56A - - GNDIO1 4-49 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function DQS VREF1_2 RUM0_PLLC_IN_A 2 T RUM0_PLLT_IN_A DQS 2 ...
Page 109
... PT44B T - PT44A C VREF1_1 PT43B - - GNDIO1 T DQS PT43A - - PT42B - - PT41A C - PT40B T - PT40A C - PT39B T D0 PT39A C D1 PT38B T VREF2_1 PT38A C - PT37B T D2 PT37A - - GNDIO1 C D3 PT36B T - PT36A C - PT35B T DQS PT35A 4-50 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function DQS ...
Page 110
... T DI PT22A C - PT21B T CSN PT21A C - PT20B T - PT20A C VREF2_0 PT19B T DQS PT19A - - PT18B - - PT17A - - GNDIO0 C - PT16B T - PT16A C - PT15B T - PT15A C - PT14B T - PT14A C - PT13B T - PT13A 4-51 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function BUSY CS1N 0 C PCLKC0_0 0 T PCLKT0_0 DQS ...
Page 111
... PT5A - - PT4B - - PT4A - - GNDIO0 - - PT3B - - CFG0 - - CFG1 - - DONE - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND - - GND 4-52 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function DQS ...
Page 112
... GND - - GND - - GND - - GND - - GND - - GND - - GND - - VCC - - VCC - - VCC - - VCC - - VCC 4-53 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ...
Page 113
... VCCAUX - - VCCAUX - - VCCAUX - - VCCAUX - - VCCAUX - - VCCIO0 - - VCCIO0 - - VCCIO0 - - VCCIO0 - - VCCIO1 - - VCCIO1 - - VCCIO1 4-54 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ...
Page 114
... Dual Ball Function Function - - VCCIO1 - - VCCIO2 - - VCCIO2 - - VCCIO2 - - VCCIO2 - - VCCIO3 - - VCCIO3 - - VCCIO3 - - VCCIO3 - - VCCIO4 - - VCCIO4 - - VCCIO4 - - VCCIO4 - - VCCIO5 - - VCCIO5 - - VCCIO5 - - VCCIO5 - - VCCIO6 - - VCCIO6 - - VCCIO6 - - VCCIO6 - - VCCIO7 - - VCCIO7 - - VCCIO7 - - VCCIO7 4-55 Pinout Information LatticeXP Family Data Sheet LFXP20 Dual Bank Differential Function ...
Page 115
... For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. • Thermal Management document • Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices • Power Calculator tool included with Lattice’s ispLEVER design tool standalone download from www.latticesemi.com/software LatticeXP Family Data Sheet 4-56 ...
Page 116
... The markings appear as follows: © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 117
... Package 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V -4 fpBGA 1.8/2.5/3.3V -5 fpBGA 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V -4 fpBGA 1.8/2.5/3.3V -5 fpBGA 5-2 Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 208 COM 3.1K 208 COM 3.1K 208 COM 3.1K 144 COM 3.1K 144 COM 3.1K 144 COM 3.1K ...
Page 118
... LFXP20C-5F388C 268 LFXP20C-3F256C 188 LFXP20C-4F256C 188 LFXP20C-5F256C 188 Part Number I/Os LFXP3E-3Q208C 136 LFXP3E-4Q208C 136 LFXP3E-5Q208C 136 LFXP3E-3T144C 100 LFXP3E-4T144C 100 LFXP3E-5T144C 100 LFXP3E-3T100C 62 LFXP3E-4T100C 62 LFXP3E-5T100C 62 Commercial (Cont.) Voltage Grade Package 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V -4 fpBGA 1.8/2.5/3.3V -5 fpBGA 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V ...
Page 119
... Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 256 COM 5.8K 256 COM 5.8K 256 COM 5.8K 208 COM 5.8K 208 COM 5.8K 208 COM 5.8K ...
Page 120
... TQFP 1.8/2.5/3.3V -4 TQFP Voltage Grade Package 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V -4 fpBGA 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V -4 fpBGA 5-5 Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 484 COM 19.7K 484 COM 19.7K 484 COM 19.7K 388 COM 19.7K 388 COM 19.7K 388 COM 19 ...
Page 121
... LFXP20C-4F484I 340 LFXP20C-3F388I 268 LFXP20C-4F388I 268 LFXP20C-3F256I 188 LFXP20C-4F256I 188 Part Number I/Os LFXP3E-3Q208I 136 LFXP3E-4Q208I 136 LFXP3E-3T144I 100 LFXP3E-4T144I 100 LFXP3E-3T100I 62 LFXP3E-4T100I 62 Part Number I/Os LFXP6E-3F256I 188 LFXP6E-4F256I 188 LFXP6E-3Q208I 142 LFXP6E-4Q208I 142 LFXP6E-3T144I 100 LFXP6E-4T144I 100 Part Number I/Os ...
Page 122
... Package 1.2V -3 fpBGA 1.2V -4 fpBGA 1.2V -3 fpBGA 1.2V -4 fpBGA 1.2V -3 fpBGA 1.2V -4 fpBGA 5-7 Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 484 IND 15.5K 484 IND 15.5K 388 IND 15.5K 388 IND 15.5K 256 IND 15.5K 256 IND 15.5K Pins Temp ...
Page 123
... Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 208 COM 3.1K 208 COM 3.1K 208 COM 3.1K 144 COM 3.1K 144 COM 3.1K 144 COM 3.1K ...
Page 124
... LFXP20C-3FN256C 188 LFXP20C-4FN256C 188 LFXP20C-5FN256C 188 Part Number I/Os LFXP3E-3QN208C 136 LFXP3E-4QN208C 136 LFXP3E-5QN208C 136 LFXP3E-3TN144C 100 LFXP3E-4TN144C 100 LFXP3E-5TN144C 100 LFXP3E-3TN100C 62 LFXP3E-4TN100C 62 LFXP3E-5TN100C 62 Part Number I/Os LFXP6E-3FN256C 188 LFXP6E-4FN256C 188 LFXP6E-5FN256C 188 LFXP6E-3QN208C 142 LFXP6E-4QN208C 142 LFXP6E-5QN208C 142 LFXP6E-3TN144C ...
Page 125
... Package 1.8/2.5/3.3V -3 fpBGA 1.8/2.5/3.3V -4 fpBGA 1.8/2.5/3.3V -3 PQFP 1.8/2.5/3.3V -4 PQFP 1.8/2.5/3.3V -3 TQFP 1.8/2.5/3.3V -4 TQFP 5-10 Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 484 COM 15.5K 484 COM 15.5K 484 COM 15.5K 388 COM 15.5K 388 COM 15.5K 388 COM 15.5K ...
Page 126
... LFXP20C-4FN484I 340 LFXP20C-3FN388I 268 LFXP20C-4FN388I 268 LFXP20C-3FN256I 188 LFXP20C-4FN256I 188 Part Number I/Os LFXP3E-3QN208I 136 LFXP3E-4QN208I 136 LFXP3E-3TN144I 100 LFXP3E-4TN144I 100 LFXP3E-3TN100I 62 LFXP3E-4TN100I 62 Part Number I/Os LFXP6E-3FN256I 188 LFXP6E-4FN256I 188 LFXP6E-3QN208I 142 LFXP6E-4QN208I 142 LFXP6E-3TN144I 100 LFXP6E-4TN144I 100 Industrial (Cont.) Voltage ...
Page 127
... Package 1.2V -3 fpBGA 1.2V -4 fpBGA 1.2V -3 fpBGA 1.2V -4 fpBGA 1.2V -3 fpBGA 1.2V -4 fpBGA 5-12 Ordering Information LatticeXP Family Data Sheet Pins Temp. LUTs 388 IND 9.7K 388 IND 9.7K 256 IND 9.7K 256 IND 9.7K Pins Temp. LUTs 484 IND 15.5K ...
Page 128
... PCI: www.pcisig.com © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 129
... DC and Switching Characteristics © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 130
... Updated Typical Building Block Function Performance timing numbers. Updated External Switching Characteristics timing numbers. Updated Internal Timing Parameters. Updated LatticeXP Family timing adders. Updated LatticeXP "C" Sleep Mode timing numbers. Updated JTAG Port Timing numbers. Added clarification to SLEEPN and TOE description. Clarification of dedicated LVDS outputs. ...