LFXP3E-3TN100I Lattice, LFXP3E-3TN100I Datasheet - Page 13

• Manufacturer Part Number: LFXP3E-3TN100I
• Description: IC FPGA 3.1KLUTS 100TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3TN100I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-10. PLL Diagram
Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block.
Figure 2-11. PLL Primitive
Table 2-5. PLL Signal Descriptions
CLKI
CLKFB
RST
CLKOS
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
Signal
CLKFB
from CLKOP
(PLL internal),
from clock net
(CLKOP) or
from a user
clock (PIN or logic)
(from routing or
external pin)
CLKI
RST
CLKFB
CLKI
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Input Clock
Divider
(CLKI)
EPLLB
Clock input from external pin or routing
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
“1” to reset input clock divider
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
Dynamic Delay Input
Dynamic Delay Zero Output
Dynamic Delay Lag/Lead Output
Dynamic Delay Output
Feedback
(CLKFB)
Divider
Dynamic Delay Adjustment
CLKOP
LOCK
Adjust
Delay
DDAIDEL[2:0]
DDA MODE
Controlled
Oscillator
DDAILAG
2-10
Voltage
DDAIZR
VCO
CLKFB
CLKI
RST
Description
Post Scalar
(CLKOP)
Divider
EHXPLLB
LatticeXP Family Data Sheet
Phase/Duty
Secondary
(CLKOK)
Divider
CLKOP
CLKOS
CLKOK
LOCK
DDAOZR
DDAOLAG
DDAODEL[2:0]
Select
Clock
Architecture
LOCK
CLKOS
CLKOP
CLKOK