LFXP3E-3TN100I Lattice, LFXP3E-3TN100I Datasheet - Page 8

• Manufacturer Part Number: LFXP3E-3TN100I
• Description: IC FPGA 3.1KLUTS 100TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3TN100I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis-
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode
in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet.
Table 2-3. Number of Slices Required for Implementing Distributed RAM
Figure 2-4. Distributed Memory Primitives
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
WRE
AD0
AD1
AD2
AD3
AD0
AD1
AD2
AD3
DI0
DI1
CK
ROM16x1
SPR16x2
Number of Slices
Note: SPR = Single Port RAM, DPR = Dual Port RAM
DO0
DO0
DO1
2-5
SPR16x2
1
WAD0
WAD1
WAD2
WAD3
WCK
WRE
DI0
DI1
DPR16x2
DPR16x2
2
LatticeXP Family Data Sheet
RAD0
RAD1
RAD2
RAD3
RDO0
RDO1
WDO0
WDO1
Architecture