LFXP3E-3TN100C LATTICE SEMICONDUCTOR, LFXP3E-3TN100C Datasheet - Page 6

• Manufacturer Part Number: LFXP3E-3TN100C
• Description: FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.2V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP3E-3TN100C

• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes

Lattice Semiconductor
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Figure 2-3. Slice Diagram
Control Signals
selected and
inverted per
slice in routing
From
Routing
Note: Some interslice signals
are not shown.
CLK
LSR
M1
M0
CE
C1
D1
C0
D0
A1
B1
A0
B0
Different slice / PFU Fast Carry Out (FCO)
Different slice / PFU Fast Carry In (FCI)
To / From
To / From
LUT4 &
CARRY
LUT4 &
CARRY
CO
CO
CI
CI
2-3
SUM
SUM
F
F
OFX0
Expansion
LUT
Mux
Slice
LatticeXP Family Data Sheet
D
D
Latch
Latch
FF/
FF/
OFX1
F1
OFX0
F0
Q0
Q1
To
Routing
Architecture