HDMP-2634

Manufacturer Part NumberHDMP-2634
ManufacturerAvago Technologies US Inc.
HDMP-2634 datasheet
 


Specifications of HDMP-2634

Operating Supply Voltage (typ)3.3VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count64
Lead Free Status / RoHS StatusNot Compliant  
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Description
This data sheet describes the
HDMP-2634 Serdes device for
2.5 GBd serial data rates.
The HDMP-2634 Serdes is a silicon
bipolar integrated circuit in a metal-
lized QFP package. It provides a
low-cost physical layer solution for
2.5 GBd serial link interfaces includ-
ing a complete Serialize/Deserialize
(Serdes) function with transmit and
receive sections in a single device.
The HDMP-2634 is also capable of
operating on 1.25 GBd serial links.
Input pins TX_RATE and RX_RATE
select the data rates on the transmit
and receive sides, respectively.
As shown in Figure 1, the transmit-
ter section accepts 10-bit wide par-
allel SSTL_2 data (TX[0:9]) and a
125 MHz SSTL_2 byte clock (TBC)
and serializes them into a high-
speed serial stream. The parallel
data is expected to be “8B/10B”
encoded data or equivalent. At the
source, TX[0:9] and TBC switch
synchronously with respect to a 125
MHz clock internal to the sender.
New data are emitted on both edges
of TBC; this is called Double Data
Rate (DDR). The HDMP-2634 finds
Agilent HDMP-2634
2.5/1.25 GBd Serdes Circuit
Data Sheet
a sampling window between the
two edges of TBC to latch TX[0:9]
data into the input register of the
transmitter section when
TX_RATE=1. If TX_RATE=0, the
user must ensure no data transi-
tions on the falling edge of TBC
and this edge is used to latch in
parallel data resulting in a 1.25
GBd serial stream.
The transmitter section’s PLL
locks to the 125 MHz TBC. This
clock is then multiplied by 20 to
generate the 2500 MHz serial
clock for the high-speed serial
outputs. The high-speed outputs
are capable of interfacing directly
to copper cables or PCB traces
for electrical transmission or to
a separate fiber optic module
for optical transmission. The
high-speed outputs include user-
controllable skin-loss equalization
to improve performance when
driving copper lines.
The receiver section accepts a
serial electrical data stream at
1.25 or 2.5 GBd and recovers
10-bit wide parallel data. The
receiver PLL locks onto the incom-
ing serial signal and recovers the
Features
• 10-bit wide parallel Tx, Rx busses
• 125 MHz TBC and RBC[0:1]
• Option to set Tx and Rx serial
data rates separately
• Parallel data I/O, clocks and
control compatible with SSTL_2
• Differential PECL or LVTTL REFCLK
at 125 MHz
• Double data rate transfers
• Source synchronous clocking of
transmit data
• Source centered or source
synchronous clocking of
receive data
• Dual or single receive byte
clocks
• Parallel loopback mode
• Differential BLL serial I/O with
on-chip source termination
• 14 mm, 64-pin MQFP package
• Single +3.3 V power supply
Applications
• Gigabit ethernet channel
aggregation trunks
• Fast serial backplanes
• Clusters
Ordering Information
Part Number
Parallel I/O
HDMP-2634
SSTL_2

HDMP-2634 Summary of contents

  • Page 1

    ... Description This data sheet describes the HDMP-2634 Serdes device for 2.5 GBd serial data rates. The HDMP-2634 Serdes is a silicon bipolar integrated circuit in a metal- lized QFP package. It provides a low-cost physical layer solution for 2.5 GBd serial link interfaces includ- ing a complete Serialize/Deserialize (Serdes) function with transmit and receive sections in a single device ...

  • Page 2

    ... The HDMP-2634 accepts either a differential PECL or a LVTTL reference clock input at 125 MHz. HDMP-2634 Block Diagram The HDMP-2634 (Figure 2) is designed to transmit and receive 10-bit wide parallel data over high-speed serial communication lines. The parallel data applied to ...

  • Page 3

    ... ASIC REFCLK[0:1] Figure 1. Typical application using HDMP-2634. TX[0:9] TBC TX PLL TXCAP0 CLOCK TXCAP1 GENERATOR RXCAP0 RXCAP1 REFCLK[0:1] TX_RATE RX_RATE RBC[0:1] RX[0:9] BYTE SYNC COM_DET Figure 2. Block diagram of HDMP-2634. 3 HDMP-2634 TRANSMITTER SECTION TX_RATE TBC TX[0:9] PLL RBC[0:1] PLL RX[0:9] COM_DET RX_RATE REF_RATE ...

  • Page 4

    FRAME MUX The FRAME MUX accepts 10-bit wide parallel data from the INPUT LATCH. Using internally generated high-speed clocks, this parallel data is multiplexed into a 2.5 GBd serial data stream. The data bits are transmitted sequen- tially from TX[0] ...

  • Page 5

    ... SSTL_2 compatible signals at the TX[0:9] and TBC pins. These pins are unterminated per section 4.1 of the SSTL_2 standard (Figure 11). The VREFT input pin is used by the HDMP-2634 to differentially detect a high or low on TBC and TX[0:9]. VREFT may be generated by the protocol device or on the PCB using a ...

  • Page 6

    ... HDMP-2634 Transmitter Section Timing Characteristics 3. 3. Symbol Parameter t TX[0:9] Input Data and TBC Clock Transition Range (TX_RATE = 1) ps TXCT t TX[0:9] Input Data and TBC Clock Valid Time (TX_RATE = 1) TXCV t TX[0:9] Setup Time to Falling Edge of TBC (TX_RATE = 0) TXSETUP t TX[0:9] Hold Time from Falling Edge of TBC (TX_RATE = 0) ...

  • Page 7

    ... SO± TX[0..9] 10-BIT CHAR B TBC Figure 4. Transmitter latency. TX[0] is first bit HDMP-2634 Receiver Section Timing Characteristics 3. 3. Symbol Parameter f_lock Frequency Lock at Powerup with REFCLK Active [1,2] b_sync Bit Sync Time [3] t_rxlat Receiver Latency Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. ...

  • Page 8

    ... Table 1. HDMP-2634 RX, RBC[0:1] Timing Dependence on RX_RATE and RBC_SYNC. Input Settings Resulting Behaviors Case RX_RATE RBC_SYNC SI Rate (GBd) RBC Rate (MHz) Timing Diagrams for RBC0, RBC1, RX[ DELAY = 0.5 - 2.0 ns SSTL_2 OUTPUT DRIVER Figure 5. Test conditions for SSTL_2 output driver. ...

  • Page 9

    RBC0 RBC1 RXS RX[0:9] Figure 5a. Receiver section timing – case A. Case A of Table 1. (RX_RATE = 0, RBC_SYNC = 3. 3. ...

  • Page 10

    RBC0 RBC1 RX[0:9] Figure 5b. Receiver section timing – case B. Case B of Table 1. (RX_RATE = 0, RBC_SYNC = 3. 3. ...

  • Page 11

    RBC0 RBC1 RX[0:9] Figure 5d. Receiver section timing – case D. Case D of Table 1. (RX_RATE = 1, RBC_SYNC = 3. 3. ...

  • Page 12

    ... CC Symbol Parameter [1] I Transceiver Supply Current (total of all supplies) CC, TRx [1] P Transceiver Total Power Dissipation D, TRx Note: 1. Measurement Conditions: Tested sending 2.5 GBd 2 resistor. HDMP-2634 PECL DC Electrical Specifications for REFCLK[ Symbol Parameter V PECL Input High Voltage Level IH,PECL V PECL Input Low Voltage Level ...

  • Page 13

    ... Parameter V LVTTL Input High Voltage Level IH,LVTTL V LVTTL Input Low Voltage Level IL,LVTTL SSTL_2 I/O Parameters HDMP-2634 Recommended DC Operating Conditions and DC Electrical Characteristics 3. 3.45 V, VDDQ = 2. 2.70 V. VDDQ is the FC-1/MAC device I/O supply voltage SSTL_2 inputs can receive LVTTL signals successfully. SSTL_2 outputs do not output LVTTL compliant levels. ...

  • Page 14

    ... HDMP-2634 Transmitter Section Output Jitter Characteristics 3. 3. Symbol Parameter [1] RJ Random Jitter [2] DJ Deterministic Jitter at SO (peak-to-peak), K28.5+/K28.5– Pattern DJ Deterministic Jitter at SO (peak-to-peak), CRPAT Notes: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH, Annex A, Section A.4.4 (oscilloscope method) and tested using the setup shown in Figure 8b ...

  • Page 15

    ... HP 70311A CLOCK SOURCE N/C CLOCK CLOCK OUT MODULATION IN 2.5 GHz Tx[0:9] HDMP-2634 TBC 2.5 GBd SERDES REFCLK 125 MHz for these devices is 38 C/W for the HDMP-2634 83480A SCOPE SO ± 10 bits HP 83480A SCOPE STATIC K28.7 0011111000 SO ± Units Typ. C/W 9.3 ...

  • Page 16

    ... HS_OUT Zo Zo ESD PROTECTION NOTE: HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT MAY ALSO BE USED. Figure 10. HS_OUT and HS_IN simplified circuit schematic for HDMP-2634. 16 (SO+) – (SO–) STEADY-STATE OUTPUT LEVEL 1.11 V STEADY-STATE OUTPUT LEVEL 820 mV 570 mV ...

  • Page 17

    ... SHOULD BE 500-1000 . 1% RESISTORS SHOULD BE USED FOR R1 AND R2. WHEN USING THE CONFIGURATION ABOVE, VREFT TO THE MAC DEVICE SHOULD BE SET TO 1.25 V NOMINAL. USING THIS VALUE CENTERS VREFR RELATIVE TO THE RX[0:9] OUTPUT SWINGS PROVIDED BY THE HDMP-2634. Figure 11. I-SSTL2 and O-SSTL2 simplified circuit schematic. I/O Type Definitions ...

  • Page 18

    ... TX_RATE 14 I-SSTL2 Transmit Rate Set: If set to low, the HDMP-2634 reads TX[0:9] data on the falling edge of TBC and serializes it. This corresponds to a 1.25 GBd serial stream. If set to high, the HDMP-2634 reads TX[0:9] data between both edges of TBC and serializes it. This corresponds to a 2.5 GBd serial stream. ...

  • Page 19

    ... VREFT 05 S Voltage Reference Input: Used with I-SSTL2 inputs to the HDMP-2634. (Figure 11.) VREFR 47 S Voltage Reference Output: Used with O-SSTL2 outputs from the HDMP-2634. (Figure 11.) V _SSTL 37 S SSTL I/O Supply Voltage for SSTL_2. Normally 3.3 V. All necessary voltages for CC 42 SSTL_2 operation are internally generated ...

  • Page 20

    ... Table 2. Pin Definitions for HDMP-2634, continued Name Pin Type Signal GND_TXHS 64 S High Speed Ground: Normally 0 volts. Used for HS_IN cell. GND_SSTL 32 S SSTL Ground: Normally 0 volts. Used for SSTL_2 I/ N Connect. Any voltage between GND and (OPTIONAL) CB11 0.1 µF ...

  • Page 21

    ... TX[6] RBC_SYNC 10 TX[7] 11 TX[8] 12 TX[9] 13 TX_RATE 14 GND_TXA 15 TXCAP1 xxxx-x = WAFER LOT NUMBER–BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE Figure 13. HDMP-2634 package layout and marking, top view HDMP-2634 41 40 xxxx-x Rz. YYWW (MARKED ON BACK OF DEVICE) ...

  • Page 22

    ... Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane Method) Mechanical Dimensions of HDMP-2634 PIN # TOP VIEW DIMENSIONAL PARAMETER (MILLIMETERS) VALUE TOLERANCE 22 Details Metric Metal QFP 85% Tin, 15% Lead 200-800 micro-inches 0.20 mm max. 0.08 mm max. ...

  • Page 23

    Data subject to change. Copyright © 2000 Agilent Technologies, Inc. December 14, 2000 5980-2107E ...