HDMP-1032

Manufacturer Part NumberHDMP-1032
ManufacturerAvago Technologies US Inc.
HDMP-1032 datasheet
 

Specifications of HDMP-1032

Operating Supply Voltage (typ)3.3VOperating Supply Voltage (min)3.15V
Operating Supply Voltage (max)3.45VOperating Temp Range0C to 150C
Operating Temperature ClassificationCommercialPackage TypePQFP
MountingSurface MountPin Count64
Lead Free Status / Rohs StatusNot Compliant  
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1.4 GBd Transmitter/Receiver Chip Set with
CIMT Encoder/Decoder and Variable Data Rate.
Description
The HDMP-1032 transmitter and
HDMP-1034 receiver are used
together to build a high-speed
data link for point-to-point
communication. These silicon
bipolar transmitter and receiver
chips are housed in standard
plastic 64 pin PQFP packages.
From the user’s viewpoint, these
products can be thought of as a
“virtual ribbon cable” interface for
the transmission of data and con-
trol words. A parallel word loaded
into the Tx (transmitter) chip is
delivered to the Rx (receiver)
chip over a serial channel and is
then reconstructed into its origi-
nal parallel form. The channel
can be either a coaxial copper
cable or optical link
The chip set hides from the
user the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding. The
CIMT encoding scheme used en-
sures the DC balance of the serial
line. When data or control words
Agilent HDMP-1032/1034
Transmitter/Receiver
Chip Set
Data Sheet
are not being sent the transmitter
sends idle words.
The serial data rate of the Tx/Rx
link is selectable in three ranges
and extends from 208 to 1120
Mbit/s. This translates into an
encoded serial rate of 260 to
1400 MBaud. The parallel data
interface is 16 bit TTL. A flag bit
is also present and can be used as
an extra 17th bit under the user’s
control. This bit can be used as
an even or odd word indicator
for dual-word transmission. The
encoding of the flag bit can be
scrambled to reduce the probabil-
ity of erroneous word alignment.
A user control space is also
provided. If TXCNTL is asserted
on the Tx chip, the least signifi-
cant 14 bits of the data will be
sent and the RXCNTL line on the
Rx chip will indicate the data is
a Control Word.
At the Rx, the PASS feature
allows the recovered words to
be clocked out with the local
Features
• 3.3 V supply, low power
dissipation
590 mW Tx, 660 mW Rx
• On-chip encode/decode using
Conditional Inversion Master
Transition (CIMT) protocol
• 1:N broadcast ready
configurable receiver inputs allow
multi-point data broadcast using a
single transmitter
• Parallel Automatic
Synchronization System (PASS)
allows receiver to read recovered
words with local reference clock
• Robust simplex mode
• Wide range serial rate
260-1400 MBaud (user selectable)
• 5 V tolerant TTL interface
16 or 17 Bits wide
• Low cost 64 pin plastic package
2
14x14 mm
PQFP
Applications
• Cellular base station
• ATM switch
• Backplane/bus extender
• Video, image acquisition
• Point to point data link
• Implement SCI-FI standard

HDMP-1032 Summary of contents

  • Page 1

    ... GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate. Description The HDMP-1032 transmitter and HDMP-1034 receiver are used together to build a high-speed data link for point-to-point communication. These silicon bipolar transmitter and receiver chips are housed in standard plastic 64 pin PQFP packages. ...

  • Page 2

    ... Tx Operation Principles – Encoding & Phase Lock Loop .................................... 24 Rx Operation Principles – Decoding & Phase Lock Loop.................................... 25 Integrator Capacitor & Power Supply Bypassing/Grounding ................................................................................................. 26 TTL and High Speed I/O ............................................................................................. 26 Data Bus Line/Broadcast Transmission ................................................................. 27 Nomenclature Changes between HDMP-1032/34 and HDMP-1022/24 .......................................................................... 30 Pin Cross Reference Table ........................................................................................ 31 Page ...

  • Page 3

    ... TXCLK C) 32 BIT SIMPLEX TRANSMISSION Tx Rx TXCLK Tx Rx TXCLK D) 32 BIT SIMPLEX TRANSMISSION Tx Rx TXCLK Rx Tx RXCLK0/1 REFCLK E) 16 BIT DUPLEX TRANSMISSION Figure 1. Various configurations using the HDMP-1032/1034 RXCLK0/1 REFCLK RXCLK0/1 REFCLK RXCLK0/1 REFCLK RXCLK0/1 REFCLK Rx DEMUX RXCLK0/1 REFCLK RXCLK0/1 REFCLK ...

  • Page 4

    ... Word 960 MBits/sec The baud rate includes an addi- tional four encoding bits (20 bits total) that the HDMP-1032/34 G-Link chipset transmits. The serial baud rate is calculated as: Serial Baud Rate = 60MW 20bits (– ...

  • Page 5

    ... TXFLAG ENCODER TXDATA TXCNTL SIGN W-FIELD TX[0-15] ENCODER Figure 3. HDMP-1032 Transmitter Block Diagram setting TCLKENB high, the user may provide an external TTL high speed serial clock at TXCLK. This clock replaces the internal VCO clock and is in- tended for diagnostic purposes only. This uncharacterized signal ...

  • Page 6

    ... HDMP-1034 Rx Block Diagram The HDMP-1034 receiver was designed to convert a serial data signal sent from the HDMP-1032 RXCAP1/0 + HSIN CDR REFCLK CLOCK GENERATOR RXCLK0/1 Figure 4 ...

  • Page 7

    Demultiplexer (DEMUX) This block takes the recovered serial data from the CDR block and demultiplexes it into a 20-bit parallel word comprised of a 16-bit word-field and 4-bit code-field. Decoder (DECODE) This block decodes the 4-bit code-field and determines whether ...

  • Page 8

    REFCLK. By adjusting the phase of the data word rather than REFCLK, the optimal setup time is achieved for the input latches of the chip interfacing to the Rx. As the relative phase between the HSIN input and ...

  • Page 9

    Multiple Channel Configuration The connections for a multiple channel configuration are shown in Figure 4.3. The daisy-chain signals SRQIN and SRQOUT are used to allow each receiver’s PASS system shift requests to propagate to the master, which is the last ...

  • Page 10

    ... TXFLAG Relative to Rising Edge of TXCLK. TXCLK TX[0-15] TXDATA TXCNTL TXFLAG t s HSOUT Figure 5. HDMP-1032 (Tx) Timing Diagram. 10 The setup and hold time param- eters, t and t , are referenced the rising edge of TXCLK. The start of a word, bit TX[0], in the high speed serial output ...

  • Page 11

    ... PASS system resets, PASSENB=1. WORD 1 W BIT 0 HSIN RXCLK1 RXCLK0 REFCLK Figure 6. HDMP-1034 (Rx) Timing Diagram. 11 RXDATA, RXCNTL and RXDSLIP are clocked out with the falling edge of RXCLK1 and appear after a delay RXCLK1 and its d complement RXCLK0 are both 50% duty cycle clocks. ...

  • Page 12

    ... HDMP-1032 (Tx), HDMP-1034 (Rx) DC Electrical Specifications Tc = – + 3.15V to 3.45V, Typical values are Symbol Parameter V TTL Input High Voltage Level, Guaranteed high signal IH,TTL for all inputs. V TTL Input Low Voltage Level, Guaranteed low signal IL,TTL for all inputs. V TTL Output High Voltage Level, I ...

  • Page 13

    ... Tc = – Symbol Parameter F TXCLK and REFCLK Frequency Tolerance tol (REFCLK is referenced to TXCLK) Symm Symmetry (Duty Cycle) HDMP-1032 (Tx), HDMP-1034 (Rx) Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent damage to A the device. Symbol Parameter V Supply Voltage CC ...

  • Page 14

    ... P ), where T is the case temperature measured on the top center of the package and 3 3 loads. All unused outputs resistor to ground. for the HDMP-1032 and HDMP-1034 is 50 C/W. jc Unit Typ. C 590 Unit Typ. C 660 is measured on a standard jc is the power being dissipated. ...

  • Page 15

    ... GND 1 TX[14] 2 TX[15] 3 TXCNTL 4 TXDATA 5 TXFLAG _TTL 8 CC GND_TTL 9 TXFLGENB 10 ESMPXENB 11 LOCKED GND Figure 7. HDMP-1032 (Tx) Package Layout, Top View. GND_TTL 1 RX[1] 2 RX[0] 3 RXREADY 4 RXERROR 5 RXDSLIP 6 V _TTL 7 CC GND_TTL GND 10 REFCLK 11 TSTCLK 12 SHFIN 13 SHFOUT 14 SRQOUT 15 V _HS 16 CC Figure 8. HDMP-1034 (Rx) Package Layout, Top View. ...

  • Page 16

    ... HDMP-1032 (Tx) Pin Definition User Mode Options Name Pin Type TXFLGENB 10 I-TTL ESMPXENB 11 I-TTL TXDATA 5 I-TTL TXCNTL 4 I-TTL High-Speed Serial/Parallel I/O HSOUT+ 20 HS_OUT HSOUT- 19 TX[0] 46 I-TTL TX[1] 47 TX[2] 50 TX[3] 51 TX[4] 52 TX[5] 53 TX[6] 54 TX[7] 55 TX[8] 58 TX[9] 59 TX[10] 60 TX[11] 61 TX[12] 62 TX[13] 63 TX[14] 2 TX[15] 3 TXFLAG ...

  • Page 17

    ... HDMP-1032 (Tx) Pin Definition (continued) PLL/Clock Generator Name Pin Type TXCAP0 32 C TXCAP1 33 TXCLK 37 I-TTL TXDIV0 26 I-TTL TXDIV1 27 LOCKED 12 O-TTL Power Supply/Ground _TTL _HS _A1 _A2 57 CC GND GND_TTL GND_HS 18 S GND_A1 30 S GND_A2 56 Test Mode/No Connect Pins TCLKENB 28 I-TTL Signal Loop Filter Capacitor: A 0.1 F min. loop filter capacitor, C2, must be connected across TXCAP0 and TXCAP1 for all combinations of TXDIV1/TXDIV0 ...

  • Page 18

    ... Enhanced Simplex Mode Enable: Enables descrambling of the Flag Bit encoding. The ESMPXENB pin on the Tx chip must be set to the same value. This mode should be enabled unless compatibility with previous versions of G-Link (i.e. HDMP-1022/1012) is desired which don’t have this feature. Enable Parallel Automatic Synchronization System: The parallel Rx data and control words are read out with REFCLK instead of the incoming word’ ...

  • Page 19

    ... HDMP-1034 (Rx) Pin Definition (continued) CDR/Clock Generator Name Pin Type RXCAP0 32 C RXCAP1 33 REFCLK 11 I-TTL RXDIV0 28 I-TTL RXDIV1 29 RXCLK0 37 O-TTL RXCLK1 38 Power Supply/Ground _TTL _HS GND GND_TTL GND_HS GND_A Signal Loop Filter Capacitor: A 0.1 F min. loop filter capacitor, C2, must be connected across RXCAP0 and RXCAP1 for all combinations of RXDIV1/RXDIV0 ...

  • Page 20

    ... HDMP-1034 (Rx) Pin Definition (continued) Pass System RXDSLIP 6 O-TTL SHFIN 13 I-TTL SHFOUT 14 O-TTL SRQIN 34 I-TTL SRQOUT 15 O-TTL Test Mode/No Connect Pins TSTCLK 12 I-TTL #RESET 35 I-TTL WSYNCDSB 36 I-TTL Word Slip: This output is asserted whenever the phase of the parallel word relative to the reference clock has exceeded the range of the internal delay, which results in a slippage of one word ...

  • Page 21

    ... Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (seating plane method) Mechanical Dimensions PIN # HDMP-103x 8 TOP VIEW Mechanical Dimensions of HDMP-1032/34 Dimensional Parameter D1/E1 (in millmeters) HDMP-103X 14.00 Tolerance 0.10 21 Details Plastic 85% Tin, 15% Lead 300–800 m 0.20 mm max 0.10 mm max ...

  • Page 22

    ... FIELD 16 BITS SERIAL BIT STREAM IDLE WORD WORD K Figure 9. HDMP-1032/1034 (Tx/Rx Pair) Line Code. 22 page. Note that the leftmost bit in each table is the first bit to be transmitted in time, while the rightmost bit is the last bit to be transmitted. Data Word Codes In Data Word mode, all 16 bits of the Tx are transmitted to the Rx, along with a flag bit ...

  • Page 23

    ... Coding with ESMPXENB=0 (Compatible with previous G-Link chips, HDMP-1012/14, HDMP-1022/24) Word Type Flag W-Field w10 w11 w12 w13 w14 w15 Data Word Structure Data = True X10 X11 X12 X13 X14 X15 1 Data = Inverted 0 #( X10 x11 X12 X13 X14 X15) 0 Data = True ...

  • Page 24

    ... TXCLK FREQUENCY DETECTOR INTERNAL CLOCKS CLOCK GENERATOR LOCK DETECT Figure 10. HDMP-1032 (Tx) Phase-Lock Loop. 24 all the internal clock signals required by the Tx chip. The data inputs, TX[0-15], as well as the control signals; TXDATA, TXCNTL and TXFLAG are latched in on the rising edge of an internally generated word rate clock ...

  • Page 25

    ... PHASE DETECTOR 1 INTERNAL CLOCKS 0 FREQUENCY DETECTOR REFCLK LOCK Figure 11. HDMP-1034 (Rx) Phase-Lock Loop. 25 • Word Decoding • Error Detection • Automatic Parallel Word Phase Adjustment Rx Data Path Figure 4 shows a simplified block diagram of the receiver. The data path consists of an Input Sampler, a Word Demultiplexer, a Coding Field (C-Field) Decoder, and a Word Field (W-Field) Decoder ...

  • Page 26

    ... HDMP-1032 BYPASS CAPACITOR C2 = PLL INTEGRATOR CAPACITOR NOTE PINS SUPPLY VOLTAGE SHOULD CC COME FROM A LOW NOISE SOURCE. Figure 12. HDMP-1032 (Tx) and HDMP-1034 (Rx) Power Supply Pins result, all of the separate power supplies ( _TTL, and _HS) can be connected onto CC this plane. The bypassing ground should be done with a ...

  • Page 27

    For opti- mum performance, both outputs should see the same impedance necessary that all HS_OUT outputs be terminated into 50 . Figure 15 shows various methods of interfacing HS_OUT to ...

  • Page 28

    ... Rx HDMP-1034 HSIN– 0.1 µF RESISTOR VALUE R1 SETS PROPER BIAS FOR THE PECL OUTPUT STAGE. THE G-LINK Rx IS INTERNALLY TERMINATED AND DOESN'T REQUIRE EXTERNAL BIAS OR TERMINATION RESISTORS PECL INPUT Tx + HDMP-1032 HDMP-1034 0.1 µF Z0 HSIN+ Z0 HSIN– 0.1 µ GENERIC PECL OUTPUT TO G-LINK Rx INPUT +5 V 0.1 µ ...

  • Page 29

    ... Figure 16. Data Bus Line Transmission HDMP-1034 HDMP-1034 Figure 17. Broadcast Transmission using a HDMP-0450 Port-Bypass Circuit Zstub 0.1 µF 0.1 µF 0.1 µ –5 V –5 V – HDMP-1034 OR HIGHER, AND NO LONGER THAN 2. INCH HDMP-1034 HDMP-1034 Zstub 0.1 µF 0.1 µ –5 V – HDMP-1034 HDMP-1034 HDMP-1032 HDMP-0450 100 ...

  • Page 30

    ... In addition, some names have been changed to names analogous to those used in Fibre Channel and Gigabit Ethernet. Examples are TXCLK instead of STRBIN and RXCLK instead of STRBOUT. A pin cross reference table for the HDMP-1032/34 & HDMP-1022/24 is provided in the table on the next page. ...

  • Page 31

    ... Pin Cross Reference Table HDMP-1032 (Tx) Pin Name 1 GND 2 TX[14] 3 TX[15] 4 TXCNTL 5 TXDATA 6 TXFLAG VCC_TTL 9 GND_TTL 10 TXFLGENB 11 ESMPXENB 12 LOCKED 13 VCC 14 GND VCC_HS 18 GND_HS 19 HSOUT- 20 HSOUT VCC 25 GND 26 TXDIV0 27 TXDIV1 28 TCLKENB GND_A1 31 VCC_A1 32 TXCAP0 33 TXCAP1 GND 36 VCC 37 TXCLK GND_TTL 41 VCC_TTL TX[0] 47 TX[1] 48 GND ...

  • Page 32

    Data subject to change. Copyright © 2000 Agilent Technologies, Inc. 5968-5909E (2/00) ...