HDMP-1032 Avago Technologies US Inc., HDMP-1032 Datasheet - Page 26

• Manufacturer Part Number: HDMP-1032
• Manufacturer: Avago Technologies US Inc.

Specifications of HDMP-1032

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 150C
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Figure 12. HDMP-1032 (Tx) and HDMP-1034 (Rx) Power Supply Pins.
Integrator Capacitor and Supply
Bypassing/Grounding
Figure 12 shows the PLL inte-
grator capacitors, power supply
capacitors and required ground-
ing for the Tx and Rx chips.
Integrator Capacitor
An integrator capacitor (C2) is
required by both the Tx and Rx
for them to function properly.
This cap is used by the PLL for
frequency and phase lock, and di-
rectly sets the stability and lockup
times. A 0.1 F capacitor is recom-
mended for each DIV1/0 setting.
Supply Bypassing/Grounding
The HDMP-1032/34 chipset has
been tested to work well with a
single power plane, assuming that
it is a fairly clean power plane. As
26
C1
C1
C1
C1
C1 = BYPASS CAPACITOR
C2 = PLL INTEGRATOR CAPACITOR
NOTE: V
COME FROM A LOW NOISE SOURCE.
CC
_A PINS SUPPLY VOLTAGE SHOULD
HDMP-1032
V
C1
C1
CC
Tx
_A2
C1
V
CC
0.1 µF
0.1 µF
_A1
a result, all of the separate power
supplies (V
V
this plane. The bypassing of V
to ground should be done with a
0.1 F capacitor (C1).
TTL and HighSpeed
I/O I-TTL and O-TTL
These I/O pins are TTL compatible.
A simplified schematic diagram of
the I/O cells is shown in Figure 13.
High-Speed Interface: HS_IN and
HS_OUT
The simplified schematic diagrams
of HS_IN and HS_OUT are shown
in Figure 14. The HS_IN input cell
is implemented with internal 50
resistors between the differential
input lines HSIN
CC
_HS) can be connected onto
C1
C2
C1
C1
CC
, V
CC
to GND_HS.
_TTL, and
C1
C1
CC
The HSIN
bias provided and the signals are
AC coupled in with 0.1 F capaci-
tors. It is recommended that
differential signals be applied
across the HSIN
15a), although a single-ended
connection is acceptable. In this
case, the unused input must be
terminated with 50 AC coupled
to ground.
The HS_OUT output cell is
designed to deliver PECL swings
directly into 50 . The output
impedance is matched to 50 and
has a VSWR of less than 2:1 to
above 2 GHz. This output is
ideal for driving the HS_IN input
through a 50
0.1 F coupling capacitor. The
HS_OUT driver can also be
HDMP-1034
C1
C1
Rx
inputs have internal
cable and a
C1
V
CC
inputs (Figure
_A
C1
C2
C1