HDMP-1032 Avago Technologies US Inc., HDMP-1032 Datasheet - Page 10

HDMP-1032

Manufacturer Part Number
HDMP-1032
Description
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HDMP-1032

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Operating Temp Range
0C to 150C
Operating Temperature Classification
Commercial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant

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HDMP-1032 (Tx) Timing
The Tx timing diagram is shown
in Figure 5. Under normal opera-
tions, the Tx PLL locks an inter-
nally generated clock to the
incoming TXCLK at which time
LOCKED is set high. The incom-
ing data, TX[0-15], TXDATA,
TXCNTL, and TXFLAG are
latched by this internal clock. The
data must be valid for t
before it is sampled and remain
valid for a time t
sampled.
Figure 5. HDMP-1032 (Tx) Timing Diagram.
10
HDMP-1032 (Tx) Timing Characteristics
Tc = –20 C to +85 C, V
Symbol
t
t
s
h
TXCLK
TX[0-15]
TXDATA
TXCNTL
TXFLAG
HSOUT
Parameter
Setup Time, for TX[0-15], TXDATA, TXCNTL and
TXFLAG Relative to Rising Edge of TXCLK.
Hold Time, for TX[0-15], TXDATA, TXCNTL and
TXFLAG Relative to Rising Edge of TXCLK.
h
after it is
CC
s
= 3.15V to 3.45V
t
s
The setup and hold time param-
eters, t
the rising edge of TXCLK.
The start of a word, bit TX[0],
in the high speed serial output
occurs after a delay of t
the rising edge of the TXCLK.
The typical value of t
approximately one clock cycle.
t
h
s
and t
h
W-FIELD
, are referenced to
t
d
d
is
d
after
Unit
nsec
nsec
C-FIELD
Min.
2.5
2.5
Typ.
Max.

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