HDMP-2634 Avago Technologies US Inc., HDMP-2634 Datasheet - Page 18

• Manufacturer Part Number: HDMP-2634
• Manufacturer: Avago Technologies US Inc.

Specifications of HDMP-2634

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Table 2. Pin Definitions for HDMP-2634
Name
EQAMP
EWRAP
EN_CDET
COM_DET
TX_RATE
RX_RATE
RBC_SYNC 10
RX_LOS
SO+
SO–
SI+
SI–
TBC
RBC[1]
RBC[0]
REFCLK[1]
REFCLK[0]
18
Pin
56
19
24
27
14
55
26
62
61
52
53
01
30
31
22
23
Type
C
I-SSTL2
I-SSTL2
O-SSTL2
I-SSTL2
I-SSTL2
I-SSTL2
O-SSTL2
HS_OUT
HS_IN
I-SSTL2
O-SSTL2
I-PECL
or
I-LVTTL
I-PECL
Signal
Output Equalization Amplitude Control: Controls the relative amount of equalization
on the high-speed serial data outputs. Equalization is disabled by connecting a 100
resistor from EQAMP to V
increasing the value (above 100 ) of a resistor connected from EQAMP to V
decreasing the value of a resistor connected from EQAMP to GND. Maximum
equalization is obtained by connecting EQAMP directly to GND. See Figure 9.
Loop Enable: When high, the high speed serial output data is internally connected
directly to the receiver circuit, bypassing the high-speed input and output buffers.
The external high-speed data outputs SO are set high and SI inputs are ignored.
Comma Detect Enable: When high, enables detection of comma character.
Comma Detect Indicator: When high, indicates that a comma character of positive
disparity (0011111xxx) has been detected on the high speed serial input line.
Transmit Rate Set: If set to low, the HDMP-2634 reads TX[0:9] data on the falling
edge of TBC and serializes it. This corresponds to a 1.25 GBd serial stream. If set to
high, the HDMP-2634 reads TX[0:9] data between both edges of TBC and serializes it.
This corresponds to a 2.5 GBd serial stream.
Receive Rate Set: If set to low, the HDMP-2634 samples the incoming serial
stream at 1.25 GBd and drives it on the RX[0:9] lines with the rising edge of RBC1. If
set to high, the HDMP-2634 samples the incoming serial stream at 2.5 GBd and
drives it on the RX[0:9] lines with the rising edges of RBC1 and RBC0. (Table 1.)
Receive Byte Clock Synchronization Control: When RBC_SYNC=1, RX[0:9] data has
the same relation to RBC[0:1] as TX[0:9] data has to TBC. ASICs designed using this
mode have the option of avoiding a SERDES driven serial link and communicating
directly on parallel lines, for short distances.
Loss of Signal at the Receiver Detect: Indicates a loss of signal on the high-speed
differential inputs, SI , as in the case where the transmission cable becomes
disconnected.
Serial Data Outputs: High speed outputs. These lines are active when not in parallel
loop mode (EWRAP=0). When EWRAP is high, these outputs are held static at logic 1.
Serial Data Inputs: High speed inputs. Serial data is accepted from SI inputs when
EWRAP is low.
Transmit Clock: Both edges of this input are used to determine the sampling window
for transmit parallel data. The transmitter section accepts this signal as the
frequency reference clock. It is multiplied by 20 to generate the outgoing serial bit
clock and other internal clocks.
Receive Byte Clocks: The receiver section recovers two receive byte clocks. These
two clocks are 180 degrees out of phase. See Table 1 for timing relationships.
Reference Clock: A 125 MHz clock supplied by the host system. It serves as the
reference clock for the receive portion of the transceiver. These pins may be driven
by a differential PECL clock source or a single ended LVTTL clock source. In the
LVTTL case, REFCLK[1] is to be driven and REFCLK[0] is to be bypassed to GND via a
0.1 F capacitor.
If SI >= 200 mV peak-to-peak differential, RX_LOS = logic 0.
If SI < 200 mV and SI > 75 mV, RX_LOS = undefined.
If SI =< 75 mV, RX_LOS = logic 1, RX[0:9]=1111111111.
CC
. The amount of equalization can be increased by either
CC
, or