FW82546EB Intel, FW82546EB Datasheet
FW82546EB
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FW82546EB Summary of contents
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Dual Port Gigabit Ethernet Controller Networking Silicon Datasheet Revision 2.1 October 2005 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Document Scope................................................................................................... 2 1.2 Reference Documents...........................................................................................2 1.3 Product Code ........................................................................................................3 2.0 Features of the 82546EB Dual Port Gigabit Ethernet Controller........................................ 4 2.1 PCI Features ......................................................................................................... 4 2.2 MAC Specific Features.......................................................................................... 4 2.3 PHY Specific Features ...
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Networking Silicon 4.2 Tristate Mode ...................................................................................................... 20 4.2.1 Tristate Mode Control and Operation ..................................................... 20 4.2.2 Tristate Mode Using JTAG (TAP)........................................................... 20 5.0 Voltage, Temperature, and Timing Specifications ........................................................... 21 5.1 Targeted Absolute Maximum Ratings ................................................................. 21 5.2 ...
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... The Intel 82546EB integrates Intel’s fourth generation gigabit MAC and PHY to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving two channels of data at rates of 1000 Mbps, 100 Mbps Mbps. In addition, it provides a 64-bit wide direct Peripheral Component Interconnect (PCI) 2 ...
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... Networking Silicon The 82546EBis packaged 364-ball grid array and footprint compatible with ® the Intel 82544GC Gigabit Ethernet Controller. Figure 1. Gigabit Ethernet Controller Block Diagram Design For Test Interface External TBI Interface LED's S/W Defined Pins 1.1 Document Scope ...
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... IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers (IEEE). ® • Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation. 1.3 Product Code The product ordering code for the 82546EB is: FW82546EB. Datasheet Networking Silicon — 82546EB 3 ...
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Networking Silicon 2.0 Features of the 82546EB Dual Port Gigabit Ethernet Controller 2.1 PCI Features PCI-X Revision 1.0a support for frequencies up to 133 MHz Multi-function PCI device PCI Revision 2.2 support for 32-bit wide or 64-bit wide ...
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PHY Specific Features Integrated PHY for 10/100/1000 Mbps full and half duplex operation IEEE 802.3ab Auto-Negotiation support IEEE 802.3ab PHY compliance and compatibility State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross- talk cancellation PHY ability to ...
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Networking Silicon 2.5 Manageability Features Manageability features on both ports: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE On-board SMB port Preboot eXecution Environment (PXE) Flash interface support (32-bit and 64-bit) Compliance with PCI Power Management ...
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... Single port or dual port implementation on the same board with minor option changes. • Offers lowest geometry to minimize power and size while maintaining Intel quality reliability standards • Lower power requirements • Extended temperature attainable with thermal management device for more demanding systems requiring a wider temperature range. Networking Silicon — ...
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... Networking Silicon 3.0 Signal Descriptions Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 3.1 Signal Type Definitions The signals of the 82546EB controller are electrically defined as follows: ...
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PCI Address, Data and Control Signals Symbol Type AD[63:0] TS CBE[7:0]# TS PAR TS PAR64 TS FRAME# STS IRDY# STS TRDY# STS Datasheet Name and Function Address and Data. Address and data signals are multiplexed on the same PCI ...
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Networking Silicon Symbol Type STOP# STS IDSEL# I DEVSEL# STS VIO P 3.2.2 Arbitration Signals Symbol Type REQ64# TS ACK64# TS REQ# TS GNT# I LOCK# I 3.2.3 Interrupt Signals Symbol Type INTA# OD INTB Name ...
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System Signals Symbol Type CLK I M66EN I RST# I LAN_ PWR_ I GOOD 3.2.5 Error Reporting Signals Symbol Type SERR# OD PERR# STS 3.2.6 Power Management Signals Symbol Type PME# OD AUX_PWR I Datasheet Name and Function The ...
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Networking Silicon 3.2.7 Impedance Compensation Signals Symbol Type ZN_COMP I/O ZP_COMP I/O 3.2.8 SMB Signals Note: A pull-up resistor with a recommended value of 4.7 KΩ should be placed along the SMB. A precise value may be calculated ...
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Flash Interface Signals Symbol Type FL_ADDR O [18:0] FL_CS# O FL_OE# O FL_WE# O FL_DATA TS [7:2] FL_DATA [1:0]/ TS LAN_DISA BLE# 3.5 Miscellaneous Signals 3.5.1 LED Signals Symbol Type ACT_A# O LINK_A# O LINKA100# O LINKA1000# O ACT_B# ...
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Networking Silicon 3.5.2 Software Definable Signals Symbol Type SDP[7:6] TS SDP[1:0] 3.6 PHY Signals 3.6.1 Crystal Signals Symbol Type XTAL1 I XTAL2 O 3.6.2 PHY Analog Signals Symbol Type REF_A P MDIA[0]+/- A MDIA[1]+/- A MDIA[2]+/- A 14 ...
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Symbol Type MDIA[3]+/- A REF_B P MDIB[0]+/- A MDIB[1]+/- A MDIB[2]+/- A MDIB[3]+/- A 3.7 Serializer / Deserializer Signals Symbol Type RXA+/- I RXB +/- TXA+/- O TXB +/- SIG_ DETECT I (A and B) Datasheet Name and Function Media ...
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Networking Silicon 3.8 JTAG Test Interface Signals Symbol Type JTAG_TCK I JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_ I TRST# CLK_VIEW O TEST# I 3.9 Power Supply Connections 3.9.1 Power Support Signals Symbol Type CTRL_15 O CTRL_25A O ...
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Ground and No Connects Symbol Type GND Reserved R Datasheet Name and Function Ground. No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins. Reserved. ...
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Networking Silicon 4.0 Test Port Functionality 4.1 XOR Testing A common board or system-level manufacturing test for proper electrical continuity between a silicon component and the board is some type of cascaded-XOR or NAND tree test. The 82546EB ...
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I/O pins with dual-mode function for XOR test: Pin Name FLSH_CE_N When XOR tree test is selected, the following pin behavior(s) occur: • Output drivers for the pins listed as tested are all placed in high-impedance (tri-state) state to ensure ...
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Networking Silicon Pins not included in XOR test tree: • JTAG (TAP) interface: TRST_N, TCK, TDO, TMS, and TDO • Test mode decode controls TEST_DM_N, EWRAP, CLK_BYP_N, CLK_VIEW, and SDP_B[7] • Each internal PHY's analog signals including PHYREF, ...
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... Voltage, Temperature, and Timing Specifications Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 5.1 Targeted Absolute Maximum Ratings Table 2. Absolute Maximum Ratings ...
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Networking Silicon Table 3. Recommended Operating Conditions Symbol Input rise/fall time (normal input) tr/tf input rise/fall time (Schmitt input) Operating temperature range TA (ambient) TJ Junction temperature a. Sustained operation of the device at conditions ...
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Table 5.b Unplugged/No Link a Typ Icc (mA Total Device 400 mW Power a. Typical conditions: operating temperature (TA nominal voltages, moderate network traffic at full duplex, and ...
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Networking Silicon Table 5.d D3cold / Wake a Typ Icc (mA Subsystem 3.3 V Current a. Typical conditions: operating temperature (TA nominal voltages, moderate network traffic ...
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TTL3 signals include: EE_DI, EE_SK, EE_CS, and JTAG_TDO. TTL6 signals include: FL_CE#, CLK_VIEW, FL_DATA[7:0], FL_ADDR[18:0], FL_OE#, and FL_WE#. TTL12 signals include: ACT_A#, ACT_B#, LINK_A#, LINK_B#, LEDA100#, LEDB100#, LEDA1000#, and LEDB1000#. 5.4 AC Characteristics Table 7. AC Characteristics: 3.3 V ...
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Networking Silicon Figure 3. AC Test Loads for General Output Pins 5.5 Serial Interface Specifications Table 12. Driver Characteristics Symbol Parameter Differential Output V OD Voltage Swing V Output Offset Voltage OS Change in V Delta V b ...
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Timing Specifications 5.6.1 PCI/PCI-X Bus Interface 5.6.1.1 PCI/PCI-X Bus Interface Clock Table 14. PCI/PCI-X Bus Interface Clock Parameters Symbol Parameter TCYC CLK cycle time TH CLK high time TL CLK low time CLK slew rate RST# slew rate a. ...
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Networking Silicon Table 15. PCI/PCI-X Bus Interface Timing Parameters Symbol Parameter Input setup time to TSU CLK: bussed signals Input setup time to TSU CLK: point-to-point (ptp) signals Input hold time from TH CLK REQ64# to RST# TRRSU ...
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Figure 6. PCI Bus Interface Input Timing Measurement Conditions PCI_CLK Input Figure 7. TVAL (max) Rising Edge Test Load Datasheet V TEST Input V TEST Valid V TL Pin 1/2 inch max. 25Ω Networking ...
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Networking Silicon Figure 8. TVAL (max) Falling Edge Test Load 5.6.2 Link Interface Timing 5.6.2.1 Link Interface Rise and Fall Time Table 16. Rise and Fall Times Symbol Parameter TR Clock rise time TF Clock fall time TR ...
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Figure 9. Link Interface Rise/Fall Timing 5.6.2.2 Link Interface Transmit Timing Figure 10. Transmit Interface Timing TX_CLOCK TX_DATA[9:0] Table 17. Transmit Interface Timing Symbol GTX_CLK period TPERIOD TBI mode (1000 Mbps) TSETUP Data setup to rising GTX_CLK THOLD Data hold ...
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Networking Silicon 5.6.2.3 Link Interface Receive Timing Figure 11. Receive Interface Timing RBC1 RX_DATA[9:0] COM_DET RBC0 Table 18. Receive Interface Timing Symbol RBC0/RBC1 frequency TREQ TBI mode (1000 Mbps) TSETUP Data setup before rising RBC0/RBC1 THOLD Data hold ...
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Flash Interface Figure 12. Flash Read Timing Flash Address [18:0] Table 19. Flash Read Operation Timing Symbol TCE Flash CE# or OE# to read data delay TACC Flash address setup time THOLD Data hold time Figure 13. Flash Write ...
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Networking Silicon Table 20. Flash Write Operation Timing Symbol TWE Flash write pulse width (WE#) TAH Flash address hold time TDS Flash data setup time 5.6.4 EEPROM Interface Table 21. Link Interface Clock Requirements Symbol TPW EE_SK pulse ...
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Package and Pinout Information 6.1 Device Identification Figure 14. 82546EB Device Identification Markings 82546EB YYWW Tnnnnnnnn (c)’ZZ Country NOTE: The black mark in the lower left corner indicates the location of pin 1. Datasheet Networking Silicon — 82546EB i ...
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Networking Silicon 6.2 Package Information The 82546EB device is a 364-lead ball grid array (BGA) measuring 21 mm dimensions are detailed in the figures below. The nominal ball pitch is 1 mm. Figure 15. 82546EB 364-Lead BGA Ball ...
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Figure 16. 82546EB Mechanical Specifications Datasheet Networking Silicon — 82546EB 37 ...
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... The use of a heat sink device can enhance the overall tolerance of higher overall ambient air temperatures is desired. Intel does not qualify or recommend any specific heat sink device for use with the 82546EB Gigabit Ethernet controller but can provide a thermal report modeling a generic heat sink device and the achieved with the use of a heat sink device ...
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Ball Mapping Diagram Note: The 82546EB device uses five categories of VDD connections: VDDO (3.3 V), AVDDH (Analog 3.3 V), AVDDL (Analog 2.5 V), and DVDD (1.5 V ...
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Networking Silicon 6.5 Pinout Information Table 24. PCI Address, Data, and Control Signals Signal PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] ...
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Table 26. Interrupt Signals Signal INTA# Table 27. System Signals Signal PCICLK M66EN Table 28. Error Reporting Signals Signal SERR# Table 29. Power Management Signals Signal PME# Table 30. Impedance Compensation Signals Signal ZN_COMP Table 31. SMB Signals Signal SMBCLK ...
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Networking Silicon Table 33. Flash Interface Signals Signal FL_ADDR[0] FL_ADDR[1] FL_ADDR[2] FL_ADDR[3] FL_ADDR[4] FL_ADDR[5] FL_ADDR[6] FL_ADDR[7] FL_ADDR[8] FL_ADDR[9] Table 34. LED Signals Signal ACT_A# LINK_A# LINKA100# Table 35. Software Definable Signals Signal SDPA[0] SDPA[1] SDPA[6] SDPA[7] Table 36. ...
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Table 37. PHY Signals Signal MDIA0+ MDIA1- MDIA1+ Table 38. Serializer / Deserializer Signals Signal RXA+ RXA- RXB+ RXB- Table 39. JTAG Test Interface Signals Signal JTAG_TCK JTAG_TDI JTAG_TDO Table 40. Power Support Signals Signal CTRL_15 Datasheet Networking Silicon — ...
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Networking Silicon Table 41. Digital Power Signals Signal VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) - PHY B VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO ...
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Table 43. Grounds and No Connect Signals Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Datasheet Networking Silicon — ...
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Networking Silicon 46 Datasheet ...