FW82546EB Intel, FW82546EB Datasheet - Page 15

• Manufacturer Part Number: FW82546EB
• Manufacturer: Intel

Specifications of FW82546EB

• Operating Supply Voltage (typ): 1.5/2.5/3.3V
• Operating Supply Voltage (min): 1.43/2.38/3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 364
• Lead Free Status / RoHS Status: Not Compliant

3.2.4
3.2.5
3.2.6
Datasheet
System Signals
Error Reporting Signals
Power Management Signals
CLK
M66EN
RST#
LAN_
PWR_
GOOD
SERR#
PERR#
PME#
AUX_PWR
Symbol
Symbol
Symbol
I
I
I
I
OD
STS
OD
I
Type
Type
Type
PCI Clock.
is an input to the
(INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other
timing parameters are defined with respect to this edge.
66 MHz Enable.
system bus is capable of supporting an operating frequency of 66 MHz.
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the
Power Management Event signal (PME#), are floated and all input signals are ignored.
The PME# context is preserved, depending on power management settings.
Most of the internal state of the 82546EB is reset on the de-assertion (rising edge) of
RST#.
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable
power is available for the 82546EB. When the signal is low, the 82546EB holds itself in
reset state and floats all PCI signals.
System Error. The System Error signal is used by the 82546EB controller to report
address parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
Parity Error. The Parity Error signal is used by the 82546EB controller to report data
parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained
tri-state and must be driven active by the 82546EB controller two data clocks after a
data parity error is detected. The minimum duration of PERR# is one clock for each
data phase a data parity error is present.
Power Management Event. The 82546EB device drives this signal low when it
receives a wake-up event and either the PME Enable bit in the Power Management
Control/Status Register or the Advanced Power Management Enable (APME) bit of the
Wake-up Control Register (WUC) is 1b.
Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available
and the 82546EB device should support the D3cold power state.
Note that AUX_PWR is not a supply input, but is an indication of whether AUX_PWR is
available to the 82546EB and/or subsystem. Setting AUX_PWR to 1b enables
advertising D3cold Wake Up support and changes the reset function of PME_En and
PME_Status. AUX_PWR is level sensitive, and any changes are immediately reflected
in the D3cold Wake Up advertisements and the PME_En and PME_Status behavior on
PCI reset.
The PCI Clock signal provides timing for all transactions on the PCI bus and
The 66 MHz Enable signal is used to indicate whether or not the
82546EB
device. All other PCI signals, except the Interrupt A
Name and Function
Name and Function
Name and Function
Networking Silicon — 82546EB
11