ICS950811AGLFT IDT, Integrated Device Technology Inc, ICS950811AGLFT Datasheet - Page 5

• Manufacturer Part Number: ICS950811AGLFT
• Description: IC FREQ GEN 200MHZ CLK 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS950811AGLFT

• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -
• Other names: 800-1818-2; 950811AGLFT

Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
0482E—08/09/07
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I
In Hardware mode it is not allowed to write to the I
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
t i
t i
0
2
3
4
5
6
7
0
2
3
4
5
6
7
1
1
4
4
4
4
5
5
P
P
, 9
, 5
, 9
, 5
, 2
, 2
5
4
4
5
3
5
3
n i
n i
-
-
-
4
5
0
4
3
5
3
4
4
4
4
5
5
#
#
8
4
8
4
1
1
C
C
C
C
C
C
C
C
C
C
C
P
3
C
C
M
C
V
P
P
P
P
P
P
P
P
C
P
P
P
P
P
U
P
E
N
6
U
U
U
U
U
S
U
U
U
U
U
U
_ I
U
U
N
L
U
6
n
a
p
C
C
C
C
F
F
_
C
C
C
C
C
C
T
F
C
C
a
S
_
_
a
-
m
e r
S
S
S
S
S
L
L
L
L
L
L
L
L
L
L
m
L
L
T
1
( T
b
K
K
K
K
0
2
T
e
K
K
K
K
K
K
E
1
a
e l
K
K
O
V /
e
O
: 2
d
T
C
T
C
T
C
T
C
L
T
C
T
C
d
P
C
0
0
2
0
2
P
0
1
2
0
1
2
) 0
1
1
#
H
#
3
2
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
P
P
W
X
W
0
0
0
0
1
1
1
X
X
X
X
X
0
0
0
1
D
2
D
C Byte 0 Bit 3.
2
2
T
T
R
R
R
R
R
R
R
R
R
y
y
R
R
R
R
R
R
p
W
W
W
p
W
W
W
W
W
W
-
e
e
1
1
R
p
R
p
R
p
H
P
S
0
1
R
C
0
n I
0
1
0
0
0
0
f o
u r
f o
u r
f o
u r
(
R
V
A
A
A
R
o
o
o
=
=
=
=
=
=
=
=
=
C
f e
f e
f e
a
f o
f e
P
C
o l l
o l l
o l l
f e
n
n
n
e
w
w
w
P
p
s
P
6
s
S
D
D
D
C
C
C
d r
_ I
U
H
n
n
n
e l
e l
e l
w t
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o t
s
o
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C
6
w
w
w
r e
r e
r e
C
p
s i
s i
s i
P
P
P
n i
n i
n i
w
_
r e
S
w
c
c
c
c
M
c
e r
S
p
2
a
C I
C I
p
U
U
U
a
a
a
S
c
g
c
g
c
g
s t
s t
s t
a
T
s t
s t
r e
u
u
u
e v
C Byte 0 Bit3. In Software mode it is not allowed to pull the
e r
H
e
b
b
b
o
o
o
T
o l
a
_
_
_
e r
h
O
L
p
p
p
L
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e l
e l
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n
n
n
h t
h t
h t
h t
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d
S
S
S
h t
O
g i
K
w
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K
d
P
m
r t
r t
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t c
d
d
d
T
T
T
m
o
h
O
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P
e
5
#
1
n
l o
l o
l o
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s
O
O
O
w
#
1
1
1
o
=
, f f
6
a v
a v
a v
d
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t o
c
c
p
P
P
P
n
=
=
=
d
f o
f o
f o
r u
6
4
r u
: e
p
n i
p
E
E
E
: e
1
#
#
#
u l
u l
u l
M
8
s
n i
m
p
e r
e r
=
o t
M
n
n
n
C
C
C
e
s
e
e
e
H
o
R
0
0
0
S
D
a
a
a
t n
a
P
P
P
t n
H
D
d
p
d
f o
f o
f o
z
=
=
=
b
b
b
f e
p
m
e
U
U
U
p
4 /
z
e
e
e l
e l
e l
N
N
N
e r
a v
s
a v
e l
e
p
C
C
C
s
F
F
F
8
c
c
d
d
d
o
o
o
d
e l
a
c
S
S
S
c
u l
L
L
L
u l
M
o
i r
4
4
4
f t
f t
f t
d
i r
s t
d
K
K
K
0
1
2
t n
e
t p
e
H
e r
e r
e r
t p
O
T
T
T
o
o r
p
p
p
h t
f o
z
f o
o i
0
e
1
e
2
e
n
n
o i
n i
n i
n i
s l
e
C /
C /
C /
n
u r
u r
u r
h t
M
P
n
s
s
s
a v
o
0
1
2
W
e
n
n
n
U
a
a
a
u
n
n
n
m
m
m
i w
i w
i w
u l
L
D
x e
p t
n i
n i
n i
T
p
p
p
e
h t
h t
h t
u
S
e t
g
g
g
e l
e l
e l
f o
l t
E
d
d
d
n r
a
a
a
v e
1
1
1
L
s s
s s
s s
o
o
o
l a
=
=
=
0
l e
n
n
n
F
F
F
e
e
e
e r
e r
e r
2
t r
t r
t r
C Byte 0 Bit 3 = 0)].
o i
o i
o i
e
e
e
n
n
n
ICS950811