MC100ES6111FA Freescale Semiconductor, MC100ES6111FA Datasheet - Page 2

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MC100ES6111FA

Manufacturer Part Number
MC100ES6111FA
Description
IC FANOUT BUFFER LV 1:10 32-LQFP
Manufacturer
Freescale Semiconductor
Series
100ESr
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of MC100ES6111FA

Number Of Circuits
1
Ratio - Input:output
2:10
Differential - Input:output
Yes/Yes
Input
ECL, HSTL, PECL
Output
ECL, PECL
Frequency - Max
2.7GHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 110°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
2.7GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100ES6111FA
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MC100ES6111FAR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 2. Function Table
MC100ES6111
2
Table 1. Pin Configuration
CLK_SEL
CLKA, CLKA
CLKB, CLKB
CLK_SEL
Q[0–9], Q[0–9]
V
V
V
1. In ECL mode (negative power supply mode), V
EE
CC
BB
CLKA
CLKA
CLKB
CLKB
power supply mode), V
referenced to the most positive supply (V
(1)
CLK_SEL
Control
Figure 1. MC100ES6111 Logic Diagram
Pin
V
V
CC
CC
Input
Input
Input
Output
Supply
Supply
Output
EE
is connected to GND (0 V) and V
Default
0
1
I/O
0
CC
).
CLKA, CLKA input pair is active. CLKA can be
driven by ECL or PECL compatible signals.
ECL/PECL
HSTL
ECL/PECL
ECL/PECL
DC
EE
V
is either –3.3 V or –2.5 V and V
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
BB
Type
CC
is either +3.3 V or +2.5 V. In both modes, the input and output levels are
V
V
Q2
Q2
Q1
Q1
Q0
Q0
CC
CC
Differential reference clock signal input
Alternative differential reference clock signal input
Active clock input select
Differential clock outputs
Negative power supply
Positive power supply. All V
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL or PECL operation
0
Figure 2. 32-Lead Package Pinout (Top View)
25
26
27
28
29
30
31
32
24
1
CC
is connected to GND (0 V). In PECL mode (positive
23
2
MC100ES6111
22
CLKB, CLKB input pair is active. CLKB can be
driven by HSTL compatible signals.
3
CC
Function
21
pins must be connected to the positive
4
Advanced Clock Drivers Devices
20
5
19
6
Freescale Semiconductor
18
1
7
17
8
16
15
14
13
12
11
10
9
V
Q7
Q7
Q8
Q8
Q9
Q9
V
CC
CC

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