MC100ES6111FA Freescale Semiconductor, MC100ES6111FA Datasheet - Page 6

• Manufacturer Part Number: MC100ES6111FA
• Description: IC FANOUT BUFFER LV 1:10 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 100ESr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MC100ES6111FA

• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: Yes/Yes
• Input: ECL, HSTL, PECL
• Output: ECL, PECL
• Frequency - Max: 2.7GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7. AC Characteristics (ECL: V
MC100ES6111
6
Clock Input Pair CLKA, CLKA (PECL or ECL differential signals)
Clock Input Pair CLKB, CLKB (HSTL differential signals)
ECL Clock Outputs (Q0-9, Q0-9)
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
3. V
4. The MC100ES6111 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.
5. V
6. V
7. Output pulse skew is the absolute difference of the propagation delay times: | t
Symbol
V
t
t
V
JIT(CC)
t
device-to-device skew.
V
propagation delay, device and part-to-part skew.
skew.
range and the input swing lies within the V
device and part-to-part skew.
sk(PP)
t
V
V
f
f
O(P-P)
sk(O)
sk(P)
t
CLK
t
CLK
t
CMR
V
r
PP
CMR
CMR
DIF
X
PD
PD
DIF
PP
, t
X
(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V
f
(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and
(AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including t
(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
(AC) range and the input swing lies within the V
Differential Input Voltage
Differential Input Crosspoint Voltage
Input Frequency
Propagation Delay CLKA or CLKB to Q0–9
Differential Input Voltage (peak-to-peak)
Differential Input Crosspoint Voltage
Input Frequency
Propagation Delay CLKB to Q0-9
Differential Output Voltage (peak-to-peak)
Output-to-Output Skew
Output-to-Output Skew (part-to-part) f
Output Cycle-to-Cycle Jitter
Output Pulse Skew
Output Rise/Fall Time
Differential Pulse
Generator
Z = 50Ω
(4)
Characteristics
(7)
(HSTL/PECL: V
(2)
(peak-to-peak)
EE
V
TT
Figure 3. MC100ES6111 AC Test Reference
Z
O
= –3.3 V ± 5% or V
DIF
= GND
= 50Ω
R
(AC) specification. Violation of V
T
(3)
(6)
= 50Ω
f
CC
O
f
f
f
O
O
O
O
< 300 MHz
(5)
< 1.5 GHz
< 2.7 GHz
< 1.5 GHz
> 1.5 GHz
= 3.3 V ± 5% or V
RMS (1σ)
PP
PECL
(AC) specification. Violation of V
EE
V
V
MC100ES6111
EE
EE
TT
= –2.5 V ± 5%, V
0.15
0.45
0.18
0.05
Min
280
280
0.4
0.3
DUT
+ 1.0
+ 0.1
.
CC
= 2.5 V ± 5%, V
X
PLH
V
V
(AC) or V
EE
EE
0.72
0.55
0.37
Typ
400
400
– t
Z
+ 0.68
+ 0.9
O
R
PHL
T
= 50Ω
CC
= 50Ω
CMR
DIF
|.
= GND) or
EE
(AC) impacts the device propagation delay,
(AC) or V
V
V
CC
EE
= GND, T
Max
0.95
0.95
0.95
530
530
150
250
1.3
2.7
1.0
2.7
0.3
35
75
1
+ 2.1
– 0.3
Advanced Clock Drivers Devices
PP
(AC) impacts the device
J
V
TT
= 0°C to +110°C)
Unit
GHz
GHz
Freescale Semiconductor
ps
ps
ps
ps
ps
ps
ps
ns
= GND
V
V
V
V
V
V
V
PD
and device-to-device
Differential
Differential
Differential
Differential
Differential
Differential
20% to 80%
Condition
(1)
X
(AC)