MK2069-04GITR IDT, Integrated Device Technology Inc, MK2069-04GITR Datasheet - Page 12

• Manufacturer Part Number: MK2069-04GITR
• Description: IC VCXO CLK TRANSLATOR 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-04GITR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

There should be no signal traces near the crystal or the
traces. Also refer to the Optional Crystal Shielding section
that follows.
4) To minimize EMI the 33 series termination resistor, if
needed, should be placed close to the clock output.
5) All components should be on the same side of the board,
minimizing vias through other signal layers (the ferrite bead
and bulk decoupling capacitor may be mounted on the
back). Other signal traces should be routed away from the
MK2069-04. This includes signal traces on PCB traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
6) Because each input selection pin includes an internal
pull-up device, those inputs requiring a logic high state (“1”)
can be left unconnected. The pins requiring a logic low state
(“0”) can be grounded.
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2 are
sensitive to noise pickup. In applications that especially
sensitive to noise, such as SONET or G-Bit ethernet
transceivers, some or all of the following crystal shielding
techniques should be considered. This is especially
important when the MK2069-04 is placed near high speed
logic or signal traces.
The following techniques are illustrated on the
Recommended PCB Layout drawing.
1) The metal layer underneath the crystal section should be
the ground layer. Remove all other layers that are above.
This ground layer will help shield the crystal circuit from
other system noise sources. As an alternative, all layers
underneath the crystal can be removed, however this is not
recommended if there are adjacent PCBs that can induce
noise into the unshielded crystal circuit.
2) Cut a channel in the PCB ground plane around the crystal
area as shown. This will eliminate high frequency ground
currents that can couple into to crystal circuit.
3) Add a through-hole for the optional third lead offered by
the crystal manufacturer (case ground). The requirement for
this third lead can be made at prototype evaluation. The
crystal is less sensitive to system noise interference when
the case is grounded.
IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
12
4) Add a ground trace around the crystal circuit to shield
from other active traces on the component layer.
The external crystal is particularly sensitive to other system
clock sources that are at or near the crystal frequency since
it will try to lock to the interfering clock source. The crystal
should be keep away from these clock sources.
The IDT Applications Note MAN05 may also be referenced
for additional suggestions on layout of the crystal section.
VCXO AND SYNTHESIZER
MK2069-04
REV J 051310