IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 17

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

Table 2: Related Bit / Register in Chapter 3.2
3
3.1
default value or status.
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
Functional Description
IDT82V3255
The reset operation resets all registers and state machines to their
After power on, the device must be reset for normal operation.
For a complete reset, the RST pin must be asserted low for at least
NOMINAL_FREQ_VALUE[23:0]
FUNCTIONAL DESCRIPTION
RESET
OSC_EDGE
Bit
NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
17
3.2
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
pin.
NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within
±741 ppm.
GR-253-CORE, ITU-T G.812 and G.813 criteria.
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
In fact, an offset from the nominal frequency may input on the OSCI
The performance of the master clock should meet GR-1244-CORE,
Register
This
MASTER CLOCK
offset
can
be
compensated
December 3, 2008
by
Address (Hex)
setting
06, 05, 04
WAN PLL
0A
the