IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 47

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

Table 34: Register List and Map (Continued)
Programming Information
IDT82V3255
Address
(Hex)
0B
7E
0C
0D
0E
1A
1D
0F
10
12
16
17
18
19
23
24
25
27
28
11
MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
PROTECTION_CNFG - Register Pro-
tection Mode Configuration
INTERRUPT_CNFG - Interrupt Config-
uration
INTERRUPTS1_STS - Interrupt Status
1
INTERRUPTS2_STS - Interrupt Status
2
INTERRUPTS3_STS - Interrupt Status
3
INTERRUPTS1_ENABLE_CNFG
Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG
Interrupt Control 2
INTERRUPTS3_ENABLE_CNFG
Interrupt Control 3
IN1_CMOS_CNFG - CMOS Input
Clock 1 Configuration
IN2_CMOS_CNFG - CMOS Input
Clock 2 Configuration
IN1_IN2_DIFF_HF_DIV_CNFG - Dif-
ferential Input Clock 1 & 2 High Fre-
quency Divider Configuration
IN1_DIFF_CNFG - Differential Input
Clock 1 Configuration
IN2_DIFF_CNFG - Differential Input
Clock 2 Configuration
IN3_CMOS_CNFG - CMOS Input
Clock 3 Configuration
PRE_DIV_CH_CNFG - DivN Divider
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
Divider Division Factor Configuration 2
IN1_IN2_CMOS_SEL_PRIORITY_CN
FG - CMOS Input Clock 1 & 2 Priority
Configuration *
IN1_IN2_DIFF_SEL_PRIORITY_CNF
G - Differential Input Clock 1 & 2 Prior-
ity Configuration *
Register Name
-
DivN
-
-
-
ATING_MO
ATING_MO
FREQ_MO
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
T0_OPER
EX_SYNC
T0_OPER
EX_SYNC
Input Clock Frequency & Priority Configuration Registers
_ALARM
_ALARM
N_CLK
IN2_DIFF_DIV[1:0]
Bit 7
DE
DE
IV
IV
IV
IV
IV
-
-
-
-
-
IN2_CMOS_SEL_PRIORITY[3:0]
IN2_DIFF_SEL_PRIORITY[3:0]
T0_MAIN_
T0_MAIN_
G_TO_TD
REF_FAIL
REF_FAIL
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOS_FLA
T4_STS
T4_STS
Bit 6
ED
ED
O
-
-
-
-
Interrupt Registers
ULTR_FAS
IN2_DIFF
IN2_DIFF
T_SW
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
Bit 5
47
-
-
-
-
-
-
-
PROTECTION_DATA[7:0]
PRE_DIVN_VALUE[7:0]
INPUT_TO
INPUT_TO
IN1_DIFF IN2_CMOS IN1_CMOS
IN1_DIFF IN2_CMOS IN1_CMOS
EXT_SW
Bit 4
_T4
_T4
-
-
-
-
-
PRE_DIVN_VALUE[14:8]
PBO_FRE
Bit 3
Z
-
-
-
-
-
-
IN1_CMOS_SEL_PRIORITY[3:0]
IN1_DIFF_SEL_PRIORITY[3:0]
PRE_DIV_CH_VALUE[3:0]
PBO_EN
Bit 2
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
-
-
-
-
-
-
HZ_EN
IN1_DIFF_DIV[1:0]
Bit 1
-
-
-
-
-
-
-
IN3_CMOS
IN3_CMOS
FREQ_MO
N_HARD_
INT_POL
December 3, 2008
Bit 0
EN
-
-
-
-
WAN PLL
Reference
Page
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