IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 45

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IDT82V3255TFG

Manufacturer Part Number
IDT82V3255TFG
Description
IC PLL WAN SMC STRATUM 3 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of IDT82V3255TFG

Input
CMOS, LVDS, PECL
Output
CMOS, LVDS, PECL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3255TFG

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5
dard except the following:
Table 33: JTAG Timing Characteristics
JTAG
IDT82V3255
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
The JTAG interface timing diagram is shown in
• The output boundary scan cells do not capture data from the
• The TRST pin is set low by default and JTAG is disabled in order
Symbol
core and the device does not support EXTEST instruction;
to be consistent with other manufacturers.
t
TCK
t
t
t
S
H
D
TCK
TMS
TDI
JTAG
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
TCK period
Parameter
TDO
t
S
Figure 17. JTAG Interface Timing Diagram
Figure
17.
t
H
45
t
TCK
Min
100
25
25
t
D
Typ
Max
50
December 3, 2008
Unit
ns
ns
ns
ns
WAN PLL

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