MC88915TFN70R2 Freescale Semiconductor, MC88915TFN70R2 Datasheet

MC88915TFN70R2

Manufacturer Part Number

MC88915TFN70R2

Description

IC DRIVER CLK PLL 70MHZ 28-PLCC

Manufacturer

Freescale Semiconductor

Type

Clock Driver, Fanout Distribution, Multiplexerr

Datasheet

1.MC88915TFN70R2.pdf (21 pages)

Specifications of MC88915TFN70R2

Pll

Yes

Input

TTL

Output

CMOS, TTL

Number Of Circuits

Ratio - Input:output

3:8

Differential - Input:output

No/No

Frequency - Max

70MHz

Divider/multiplier

Yes/Yes

Voltage - Supply

4.75 V ~ 5.25 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

70MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

MC88915TFN70R2TR

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MC88915TFN70R2

Manufacturer:

Freescale Semiconductor

Quantity:

10 000

Current page: 1 of 21
Download datasheet (156Kb)

SEMICONDUCTOR TECHNICAL DATA

55, 70, 100, 133 and 160MHz Versions

lock its low skew outputs’ frequency and phase onto an input reference

clock. It is designed to provide clock distribution for high performance PC’s

and workstations. For a 3.3V version, see the MC88LV915T data sheet.

clock input and distribute it with essentially zero delay to multiple

components on a board. The PLL also allows the MC88915T to multiply a

low frequency input clock and distribute it locally at a higher (2X) system

frequency. Multiple 88915’s can lock onto a single reference clock, which is

ideal for applications when a central system clock must be distributed

synchronously to multiple boards (see Figure 7).

phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”

frequency.

the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the

“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on

page 2). In most applications FREQ_SEL should be held high ( 1). If a low frequency reference clock input is used, holding

FREQ_SEL low ( 2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).

88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency

board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see

detailed description on page 11).

OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC

input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.

low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a

SYNC signal and full 5V V

Features

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

The MC88915T Clock Driver utilizes phase–locked loop technology to

The PLL allows the high current, low skew outputs to lock onto a single

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180

The VCO is designed to run optimally between 20 MHz and the 2X_Q F

The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the

A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go

Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t

specification, which defines the part–to–part skew)

Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)

Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180 phase shift) output available

All outputs have 36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are

TTL–level compatible. 88mA I

Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3–state) for board test purposes

Lock Indicator (LOCK) accuracy indicates a phase–locked state

Motorola, Inc. 2001

specifications guarantee 50

transmission line switching on the incident edge

max

specification. The wiring diagrams in Figure 5 detail

PLL CLOCK DRIVER

LOW SKEW CMOS

Order Number: MC88915T/D

Rev 5, 08/2001

Related parts for MC88915TFN70R2

MC88915TFN70R2 Summary of contents

Page 1

SEMICONDUCTOR TECHNICAL DATA 55, 70, 100, 133 and 160MHz Versions The MC88915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock designed to provide clock distribution for ...

Page 2

PIN SUMMARY 2 Pinout: 28–Lead PLCC (Top View) FN SUFFIX PLASTIC PLCC CASE 776–02 MOTOROLA ...

Page 3

Figure 1. MC88915T Block Diagram (All Versions) MOTOROLA 3 ...

Page 4

MC88915TFN55 and MC88915TFN70 SYNC INPUT TIMING REQUIREMENTS Symbol t ,SYNC Inputs Rise/Fall Time, SYNC Inputs RISE/FALL From 0 SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs 1. ...

Page 5

MC88915TFN55 and MC88915TFN70 FREQUENCY SPECIFICATIONS (T =– + Symbol 1 f Maximum Operating Frequency (2X_Q Output) max Maximum Operating Frequency (Q0–Q4,Q5 Output) 1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, ...

Page 6

SYNC INPUT TIMING REQUIREMENTS Symbol t ,SYNC Inputs Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V RISE/FALL t , SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs 1. These t minimum ...

Page 7

AC CHARACTERISTICS (T =– + Symbol Parameter t Rise/Fall Time, All Outputs RISE/FALL Outputs (Between 0.2V and 0. Rise/Fall Time Into a 20pF Load, With Ter- RISE/FALL 2X_Q Output mination Specified in ...

Page 8

Page 9

Page 10

Page 11

AC CHARACTERISTICS ( + Symbol Parameter t Rise/Fall Time, All Outputs RISE/FALL Outputs (Between 0.2V and 0. Rise/Fall Time RISE/FALL 2X_Q Output t Output Pulse Width: Q0, Q1, Q2, Q3, Q4, PULSE ...

Page 12

Applications Information for All Versions General AC Specification Notes 1. Several specifications can only be measured when the MC88915TFN55, 70 and 100 are in phase–locked operation not possible to have the part in phase–lock on ATE (automated test ...

Page 13

Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is Present When The t specification guarantees that the rising edges SKEWr of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall within ...

Page 14

Calculation of Total Output–to–Skew between multiple parts (Part–to–Part skew) By combining the t specification and the information in PD Note 5, the worst case output–to–output skew between multiple 88915’s connected in parallel can be calculated. This calculation assumes that ...

Page 15

The lock indicator pin (LOCK) will reliably indicate a phase–locked condition at SYNC input frequencies down to 10MHz. At frequencies below 10MHz, the frequency of correction pulses going into the phase detector form the SYNC and FEEDBACK pins may ...

Page 16

Figure 4. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook–up configuration of Figure 5a on page 17) Timing Notes: The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not ...

Page 17

Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back MOTOROLA 17 ...

Page 18

Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T Notes Concerning Loop Filter and Board Layout Issues 1. Figure 6 shows a loop filter and analog isolation scheme which will be effective in most applications. The following ...

Page 19

Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915T for Frequency Multiplication and Low Board–to–Board Skew MC88915T System Level Testing Functionality 3–state functionality has been added to the 100MHz version of the MC88915T to ease system board testing. ...

Page 20

OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776–02 ISSUE BRK –M– VIEW D– –T– VIEW S VIEW ...

Page 21

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

Related keywords

mc88915
mc88915t
mc88915fn
mc88915fn70
mc88915fn55
mc88916
mc88915tfn70
mc88915tfn55
mc88915tfn133
mc88915tfn100
mc88915fn55r2
mc88920
mc88915tfn160
MC88915TFN70R2 datasheet
MC88915TFN70R2 data sheet
MC88915TFN70R2 pdf datasheet
MC88915TFN70R2 component
MC88915TFN70R2 part
MC88915TFN70R2 distributor
MC88915TFN70R2 RoHS
MC88915TFN70R2 datasheet download