MC88915TFN70R2 Freescale Semiconductor, MC88915TFN70R2 Datasheet - Page 7

• Manufacturer Part Number: MC88915TFN70R2
• Description: IC DRIVER CLK PLL 70MHZ 28-PLCC
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MC88915TFN70R2

• Pll: Yes
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:8
• Differential - Input:output: No/No
• Frequency - Max: 70MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 70MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC88915TFN70R2TR

AC CHARACTERISTICS
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T
3. The T
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V
6. The t
t
Outputs
t
2X_Q Output
t
(Q0–Q4, Q5, Q/2)
t
(2X_Q Output)
t
(2X_Q Output)
t
SYNC F
SYNC Feedback
t
(Rising) See Note
t
(Falling)
t
t
t
t
RISE/FALL
RISE/FALL
PULSE WIDTH
PULSE WIDTH
PULSE WIDTH
PD
SKEWr
SKEWf
SKEWall
LOCK
PZL
PHZ
MOTOROLA
C1 = 0.01 F.
CYCLE
1,3
6
,t
5
PLZ
Symbol
PZL
1,4
1,4
1,4
PD
CC
6
1
in this spec is 1/Frequency at which the particular output is running.
, t
db
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
fully powered–on, and an output properly connected to the FEEDBACK pin. t
PHZ
1
1
1
, t
k
PLZ
5
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
Rise/Fall Time, All Outputs
(Between 0.2V
Rise/Fall Time Into a 20pF Load, With Ter-
mination Specified in Note
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
Q5, Q/2 @ V
Output Pulse Width:
2X_Q @ 1.5V
Output Pulse Width:
2X_Q @ V
SYNC Input to Feedback Delay
(M
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
FEEDBACK In ut Pins)
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
(T
A
=–40 C to +85 C, V
d t SYNC0
CC
CC
/2
CC
Parameter
/2
and 0.8V
1
MC88915TFN100
2
CC
66–100MHz
d
CC
)
40–49MHz
50–65MHz
= 5.0V 5%, Load = 50 Terminated to V
0.5t
0.5t
0.5t
0.5t
0.5t
(With 1M from RC1 to An GND)
(With 1M from RC1 to An V
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
+1.25
–1.05
Min
1.0
0.5
1.0
3.0
3.0
—
—
—
(continued)
– 0.5
– 0.5
– 1.5
– 1.0
– 0.5
2
2
2
LOCK
0.5t
0.5t
0.5t
0.5t
0.5t
maximum is with C1 = 0.1 F, t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
–0.30
+3.25
Max
CC
500
500
750
2.5
1.6
10
14
14
/2)
+ 0.5
+ 0.5
+ 1.5
CC
+ 1.0
+ 0.5
)
2
2
2
Unit
ms
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
Into a 50 Load
Terminated to V
t
t
Into a 50 Load
Terminated to V
Must Use Termination
Specified in Note 2
Into a 50 Load
Terminated to V
See Note 4 and
Fi
Figure 2 for Detailed
Explanation
Ex lanation
All Outputs Into a
Matched 50 Load
Terminated to V
All Outputs Into a
Matched 50 Load
Terminated to V
All Outputs Into a
Matched 50 Load
Terminated to V
Also Time to LOCK
Indicator High
Measured With the
PLL_EN Pin Low
Measured With the
PLL_EN Pin Low
RISE
FALL
LOCK
: 0.8V – 2.0V
: 2.0V – 0.8V
Condition
2 f
minimum is with
D t il d
CC
CC
CC
CC
CC
CC
7
/2
/2
/2
/2
/2
/2