MPC9772FA Freescale Semiconductor, MPC9772FA Datasheet - Page 9

• Manufacturer Part Number: MPC9772FA
• Description: IC CLOCK GEN PLL LV 1:12 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9772FA

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC9772 Individual Output Disable (Clock Stop) Circuitry
MPC9772 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC9772 clock
outputs can be individually stopped in the logic ‘0' state: The
clock stop mechanism allows serial loading of a 12-bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
writing logic ‘0' to the respective stop enable bit. Likewise, the
TIMING SOLUTIONS
The individual clock stop (output enable) control of the
The user can program an output clock to stop (disable) by
STOP_DATA
STOP_CLK
START
Freescale Semiconductor, Inc.
QA0
For More Information On This Product,
Figure 5. Clock Stop Circuit Programming
QA1
Go to: www.freescale.com
QA2
QA3
9
QB0
user may programmably enable an output clock by writing logic
‘1' to the respective enable bit. The clock stop logic enables or
disables clock outputs during the time when the output would be
in normally in logic low state, eliminating the possibility of short
or ‘runt' clock pulses.
STOP_DATA input by supplying a logic ‘0' start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free-running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC9772 can sample each
STOP_DATA bit with the rising edge of the free-running
STOP_CLK signal. (See Figure 5.)
QB1
The user can write to the serial input register through the
QB2
QB3
QC1
QC2
QC3
QSYNC
MPC9772
MOTOROLA