LMX2324SLBX National Semiconductor, LMX2324SLBX Datasheet - Page 8

• Manufacturer Part Number: LMX2324SLBX
• Description: IC FREQ SYNTH 2.0GHZ 16LAMINATE
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2324SLBX

• Pll: Yes
• Input: CMOS, TTL
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-Laminate CSP
• Frequency-max: 2GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2324SLBX; LMX2324SLBXTR

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Regist
er
Divide
2.3 N REGISTER
If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit N
register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the
control word. Serial data format is shown below in tables 2.3.1 and 2.3.2. The pulse swallow function which determines the divide
ratio is described in section 2.3.3. Data is clocked into the shift register MSB first.
2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)
Notes: Swallow Counter Value: 0 to 31
NB_CNTR
2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)
Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited)
NB_CNTR
2.3.3 Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P (B - A) times. The B value
(NB_CNTR) must be
as the binary counter value is greater than the swallow counter value (NB_CNTR
f
N = (P x B) + A
f
f
R:
N:
B:
A:
P:
Swallow Count
Ratio
N
VCO
VCO
OSC
1023
3
4
•
:
:
= N x (f
MSB
N16 N15 N1
(A)
31
17
0
1
•
Output frequency of external voltage controlled oscillator (VCO)
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)
Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
Preset value of binary 5-bit swallow A counter (0
Preset modulus of dual modulus prescaler (P=32)
≥
≥
NA_CNTR
NA_CNTR
OSC
16
N16
0
0
1
•
/R)
15
4
≥
3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long
N13
14
N15
0
0
1
•
N6
0
0
1
•
N12
13
NB_CNTR[9:0]
101030 Version 8 Revision 1
N14
0
0
1
•
N11
12
SHIFT REGISTER BIT LOCATION
N13
0
0
1
N5
•
0
0
1
•
N10
NB_CNTR[10:0]
11
≤
A
Data Field
N12
≤
Print Date/Time: 2010/03/17 20:00:58
0
0
1
8
•
N9
10
31, A
NA_CNTR[4:0]
N8
9
≤
B)
N4
N11
0
0
1
•
N7
0
0
1
•
8
N6
≥
7
NA_CNTR).
NA_CNTR[4:0]
N10
N5
6
0
0
1
•
N4
5
N3
0
0
1
•
N3
4
N9
0
1
1
•
N2
3
CTL_WORD
N1
N8
2
1
0
1
•
[1:0]
N2
0
1
1
N0
•
1
N7
1
0
1
•
LSB
ADD
Field
0
R
0