ISL1208IB8Z-TKR5291 Intersil, ISL1208IB8Z-TKR5291 Datasheet - Page 13

• Manufacturer Part Number: ISL1208IB8Z-TKR5291
• Description: IC RTC LP BATT BACKED SRAM 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL1208IB8Z-TKR5291

• Memory Size: 2B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/fOUT pin. See
Table 4 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/fOUT pin.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the fOUT/IRQ pin during battery
backup mode (i.e. V
FOBATB is set to “1” the fOUT/IRQ pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the fOUT/IRQ pin is enabled
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
power mode and the V
V
about 600nA when using LPMODE = “1” with V
(See Typical Performance Curves on page 7: I
with LPMODE ON and OFF.) Avoid setting the device into
low power mode with V
will stop permanently. The V
below V
FREQUENCY,
BAT
DD
DD
32768
< V
< V
f
4096
1024
1/16
1/32
OUT
supply will be used when V
1/2
1/4
1/8
64
32
16
TABLE 4. FREQUENCY SELECTION OF fOUT PIN
0
8
4
2
1
DD
TRIP
BAT
to resume communications.
. With LPMODE = “1”, the device will be in low
- V
UNITS
BATHYS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
BAT
BAT
DD
. There is a supply current saving of
power source active). When the
FO3
< V
supply will be used when
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BAT
13
BAT
input must be lowered
DD
, the I2C communications
FO2
< V
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BAT
- V
FO1
DD
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DD
BATHYS
vs V
= 5V.
FO0
CC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
and
ISL1208
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/fOUT pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/fOUT pin will be
tied low until the ALM status bit is cleared to “0”.
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to
-94ppm to +140ppm of total adjustment.
The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
controlled capacitors, C
and X2 pins to ground (see Figure 11). The value of C
C
C X
X2
=
are given in Equation 1:
(
IM BIT
16 b5
0
1
⋅
+
8 b4
X1
X2
FIGURE 11. DIAGRAM OF ATR
⋅
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
LOAD
+
4 b3
C
C
X1
X2
⋅
INTERRUPT/ALARM FREQUENCY
X1
is changed via two digitally
+
and C
2 b2
⋅
+
X2
1 b1
OSCILLATOR
⋅
, connected from the X1
CRYSTAL
+
0.5 b0
⋅
September 12, 2008
+
9
LOAD
)pF
X1
,
FN8085.8
(EQ. 1)
and